公开(公告)号：US08698118B2

公开(公告)日：2014-04-15

申请号：US13408221

申请日：2012-02-29

申请人： Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

发明人： Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

IPC分类号： H01L29/02 ,  H01L47/00 ,  H01L29/04 ,  H01L29/06

CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147

摘要： Disclosed herein is a compact RRAM (Resistance Random Access Memory) device structure and various methods of making such an RRAM device. In one example, a device disclosed herein includes a gate electrode, a conductive sidewall spacer and at least one variable resistance material layer positioned between the gate electrode and the conductive sidewall spacer.

摘要翻译： 这里公开了紧凑的RRAM（电阻随机存取存储器）装置结构和制造这种RRAM装置的各种方法。 在一个示例中，本文公开的器件包括栅极，导电侧壁隔离物和位于栅电极和导电侧壁间隔物之间​​的至少一个可变电阻材料层。

公开(公告)号：US08674332B2

公开(公告)日：2014-03-18

申请号：US13445658

申请日：2012-04-12

申请人： Eng Huat Toh ,  Shyue Seng Tan ,  Elgin Quek

发明人： Eng Huat Toh ,  Shyue Seng Tan ,  Elgin Quek

IPC分类号： H01L29/02 ,  H01L47/00

CPC分类号： H01L45/04 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1666

摘要： One device disclosed herein includes first and second sidewall spacers positioned above a semiconducting substrate, wherein the first and second sidewall spacers are comprised of at least a conductive material, a conductive word line electrode positioned between the first and second sidewall spacers and first and second regions of variable resistance material positioned between the conductive word line electrode and the conductive material of the first and second sidewall spacers, respectively. This example also includes a base region of a bipolar transistor in the substrate below the word line electrode, an emitter region formed below the base region and first and second collector regions formed in the substrate within the base region, wherein the first collector region is positioned at least partially under the first region of variable resistance material and the second collector region is positioned at least partially under the second region of variable resistance material.

摘要翻译： 本文公开的一种装置包括位于半导体衬底之上的第一和第二侧壁间隔物，其中第一和第二侧壁间隔物由至少导电材料构成，位于第一和第二侧壁间隔物之间​​的导电字线电极和第一和第二区域 分别位于导电字线电极和第一和第二侧壁间隔物的导电材料之间的可变电阻材料。 该示例还包括在字线电极下方的基板中的双极晶体管的基极区域，形成在基极区域下方的发射极区域和形成在基极区域内的基板中的第一和第二集电极区域，其中第一集电极区域被定位 至少部分地在可变电阻材料的第一区域下方，并且第二集电极区域至少部分地位于可变电阻材料的第二区域的下方。

公开(公告)号：US20140008713A1

公开(公告)日：2014-01-09

申请号：US13543340

申请日：2012-07-06

申请人： Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

发明人： Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

IPC分类号： H01L21/8239 ,  H01L27/088

CPC分类号： H01L21/823437 ,  H01L21/28273 ,  H01L21/823425 ,  H01L21/823468 ,  H01L27/11524 ,  H01L29/66545

摘要： A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with RMG processes. Embodiments include forming a first and a second dual polysilicon gate-stack structure on an upper surface of a substrate, forming spacers on opposite sidewalls of each of the first and the second dual polysilicon gate-stack structures, forming an ILD adjacent to an exposed sidewall of each spacer, removing the first dual polysilicon gate-stack structure, forming a first cavity between the spacers, and forming a HKMG in the first cavity, wherein the HKMG forms an access gate.

摘要翻译： 通过集成嵌入式非易失性存储器（eNVM）与RMG进程来制造存储器件。 实施例包括在衬底的上表面上形成第一和第二双多晶硅栅叠层结构，在第一和第二双多晶硅栅叠层结构中的每一个的相对侧壁上形成间隔物，形成与露出侧壁相邻的ILD 移除所述第一双多晶硅栅堆叠结构，在所述间隔物之间​​形成第一空腔，并在所述第一空腔中形成HKMG，其中所述HKMG形成存取栅极。

公开(公告)号：US20130270501A1

公开(公告)日：2013-10-17

申请号：US13445658

申请日：2012-04-12

申请人： Eng Huat Toh ,  Shyue Seng Tan ,  Elgin Quek

发明人： Eng Huat Toh ,  Shyue Seng Tan ,  Elgin Quek

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L45/04 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1666

摘要： One device disclosed herein includes first and second sidewall spacers positioned above a semiconducting substrate, wherein the first and second sidewall spacers are comprised of at least a conductive material, a conductive word line electrode positioned between the first and second sidewall spacers and first and second regions of variable resistance material positioned between the conductive word line electrode and the conductive material of the first and second sidewall spacers, respectively. This example also includes a base region of a bipolar transistor in the substrate below the word line electrode, an emitter region formed below the base region and first and second collector regions formed in the substrate within the base region, wherein the first collector region is positioned at least partially under the first region of variable resistance material and the second collector region is positioned at least partially under the second region of variable resistance material.

摘要翻译： 本文公开的一种装置包括位于半导体衬底之上的第一和第二侧壁间隔物，其中第一和第二侧壁间隔物由至少导电材料构成，位于第一和第二侧壁间隔物之间​​的导电字线电极和第一和第二区域 分别位于导电字线电极和第一和第二侧壁间隔物的导电材料之间的可变电阻材料。 该示例还包括在字线电极下方的基板中的双极晶体管的基极区域，形成在基极区域下方的发射极区域和形成在基极区域内的基板中的第一和第二集电极区域，其中第一集电极区域被定位 至少部分地在可变电阻材料的第一区域下方，并且第二集电极区域至少部分地位于可变电阻材料的第二区域的下方。

公开(公告)号：US20130240821A1

公开(公告)日：2013-09-19

申请号：US13423793

申请日：2012-03-19

申请人： Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

发明人： Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

IPC分类号： H01L45/00 ,  H01L21/8239

CPC分类号： H01L27/2409 ,  H01L27/2445 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

摘要： Disclosed herein are various embodiments of novel three dimensional RRAM devices, and various methods of making such devices. In one example, a device disclosed herein includes a first electrode for a first bit line comprising a variable resistance material, a second electrode for a second bit line comprising a variable resistance material and a third electrode positioned between the variable resistance material of the first bit line and the variable resistance material of the second bit line.

摘要翻译： 本文公开了新型三维RRAM设备的各种实施例以及制造这些设备的各种方法。 在一个示例中，本文公开的装置包括用于第一位线的第一电极，其包括可变电阻材料，用于第二位线的第二电极，包括可变电阻材料和位于第一位的可变电阻材料之间的第三电极 线和第二位线的可变电阻材料。

公开(公告)号：US08470700B2

公开(公告)日：2013-06-25

申请号：US12804487

申请日：2010-07-22

申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Shiang Yang Ong ,  Elgin Quek

发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Shiang Yang Ong ,  Elgin Quek

IPC分类号： H01L21/26

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/28556 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/66575

摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

公开(公告)号：US08368127B2

公开(公告)日：2013-02-05

申请号：US12587511

申请日：2009-10-08

申请人： Ming Zhu ,  Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek

发明人： Ming Zhu ,  Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek

IPC分类号： H01L29/76

CPC分类号： H01L21/26586 ,  B82Y10/00 ,  H01L29/0895 ,  H01L29/7391 ,  H01L29/7606 ,  H01L29/7613

摘要： A method (and semiconductor device) of fabricating a TFET device provides a source region having at least a portion thereof positioned underneath a gate dielectric. In one embodiment, the TFET includes an N+ drain region and a P+ source region in a silicon substrate, where the N+ drain region is silicon and the P+ source region is silicon germanium (SiGe). The source region includes a first region of a first type (e.g., P+ SiGe) and a second region of a second type (undoped SiGe), where at least a portion of the source region is positioned below the gate dielectric. This structure decreases the tunneling barrier width and increases drive current (Id).

摘要翻译： 制造TFET器件的方法（和半导体器件）提供了一个源极区，其源极区至少有一部分位于栅极电介质的下面。 在一个实施例中，TFET在硅衬底中包括N +漏极区域和P +源极区域，其中N +漏极区域是硅并且P +源极区域是硅锗（SiGe）。 源区包括第一类型的第一区域（例如，P + SiGe）和第二类型（未掺杂的SiGe）的第二区域，其中源极区域的至少一部分位于栅极电介质的下方。 该结构降低了隧道势垒宽度并增加了驱动电流（Id）。

公开(公告)号：US20120292707A1

公开(公告)日：2012-11-22

申请号：US13108439

申请日：2011-05-16

申请人： Eng Huat Toh ,  Elgin Quek ,  Chung Foong Tan

发明人： Eng Huat Toh ,  Elgin Quek ,  Chung Foong Tan

IPC分类号： H01L21/336 ,  H01L29/78 ,  B82Y99/00

CPC分类号： H01L29/685 ,  B81B3/0081 ,  B81B2203/0109 ,  B81B2207/015 ,  B82Y10/00 ,  G11C11/56 ,  G11C23/00 ,  G11C2213/16 ,  H01L21/28282 ,  H01L21/764 ,  H01L27/1052 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/1104 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

摘要： Semiconductor devices are formed with a nano-electro-mechanical system (NEMS) logic or memory on a bulk substrate. Embodiments include forming source/drain regions directly on a bulk substrate, forming a fin connecting the source/drain regions, forming two gates, one on each side of the fin, the two gates being insulated from the bulk substrate, and forming a substrate gate in the bulk substrate. The fin is separated from each of the two gates and the substrate gate with an air gap.

摘要翻译： 半导体器件由体积衬底上的纳米机电系统（NEMS）逻辑或存储器形成。 实施例包括直接在体基板上形成源极/漏极区域，形成连接源极/漏极区域的鳍片，形成两个栅极，鳍片的每一侧上一个，两个栅极与本体衬底绝缘，以及形成衬底栅极 在散装衬底中。 翅片与具有气隙的两个栅极和衬底栅极中的每一个分离。

公开(公告)号：US20120228705A1

公开(公告)日：2012-09-13

申请号：US13046332

申请日：2011-03-11

申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

摘要： An LDMOS is formed with a second gate stack over the n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.

摘要翻译： LDMOS在n漂移区上形成有第二栅极堆叠，其具有与栅极堆叠相同的公共栅电极，并且具有比栅极堆叠更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二栅极叠层， 第二阱，第一和第二栅极堆叠共享公共栅极电极，并且调谐第一和第二栅极堆叠的功函数以获得用于第二栅极堆叠的较高功函数。 其他实施例包括用第一高k电介质形成第一栅极堆叠，以及用第二高k电介质形成第二栅极堆叠，以及用不对称电介质形成第一和第二栅极堆叠。

公开(公告)号：US20120228695A1

公开(公告)日：2012-09-13

申请号：US13046313

申请日：2011-03-11

申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

摘要： An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.

摘要翻译： LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层， 分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。 其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成 栅极堆叠彼此分离并具有不同的栅极电介质材料。