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    Virtual Ground Non-volatile Memory Array
    21.
    发明申请
    Virtual Ground Non-volatile Memory Array 审中-公开
    虚拟地面非易失性存储器阵列

    公开(公告)号：US20160133639A1

    公开(公告)日：2016-05-12

    申请号：US14935201

    申请日：2015-11-06

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

    IPC: H01L27/115 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04

    CPC classification number: H01L27/11526 ,  G11C16/0408 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

    Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

    Abstract translation: 一种存储器件，具有每个具有单个连续沟道区的存储单元对，在沟道区的第一和第二部分上的第一和第二浮置栅极，位于第一和第二沟道区域之间的沟道区的第三部分上的擦除栅极， 以及第一和第二浮动栅极上的第一和第二控制栅极。 对于每对存储器单元，第一区域电连接到相同有源区域中相邻的一对存储器单元的第二区域，并且第二区域电连接到相邻存储器对的第一区域 细胞在相同的活性区域。

    Non-volatile Split Gate Memory Device And A Method Of Operating Same
    22.
    发明申请
    Non-volatile Split Gate Memory Device And A Method Of Operating Same 有权

    公开(公告)号：US20160099067A1

    公开(公告)日：2016-04-07

    申请号：US14506433

    申请日：2014-10-03

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

    IPC: G11C16/24 ,  G11C16/26 ,  G11C16/04 ,  G11C16/14

    CPC classification number: G11C16/24 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

    Abstract: A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage. A control circuit receives a command signal and generates a plurality of control signals, in response thereto and applies the first negative voltage to the word line of the unselected memory cells. During the operations of program, read or erase, a negative voltage can be applied to the word lines of the unselected memory cells.

    Flash memory system using complementary voltage supplies
    25.
    发明授权
    Flash memory system using complementary voltage supplies 有权

    公开(公告)号：US10186322B2

    公开(公告)日：2019-01-22

    申请号：US15361473

    申请日：2016-11-27

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC: G11C16/30 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C5/14 ,  G11C8/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521

    Abstract: A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.

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