公开(公告)号：US07843050B2

公开(公告)日：2010-11-30

申请号：US11863425

申请日：2007-09-28

申请人： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon

发明人： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon

IPC分类号： H01L23/02

CPC分类号： H01L25/105 ,  H01L21/50 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49555 ,  H01L23/49811 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/17 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16258 ,  H01L2224/17106 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

摘要： Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.

摘要翻译： 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，堆叠封装的系统包括具有底侧的第一裸片封装，第一电介质外壳和第一金属引线; 具有附接到第一封装的底侧的顶侧的第二管芯封装，具有侧面的电介质外壳和与第一金属引线对准并朝向第一金属引线突出的第二金属引线，并且包括外表面和内表面区域， 一般面向外侧; 和金属焊接连接器将各个第一引线连接到单独的第二引线。 在另一个实施例中，各个第二引线具有“L”形状并且物理地接触相应的单个第一引线。 在另一个实施例中，各个第二引线具有“C”形并且包括向第二壳体的侧面突出的分层部分。

公开(公告)号：US20090014858A1

公开(公告)日：2009-01-15

申请号：US11846928

申请日：2007-08-29

申请人： Suan Jeung Boon ,  Meow Koon Eng ,  Yong Poo Chia

发明人： Suan Jeung Boon ,  Meow Koon Eng ,  Yong Poo Chia

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L23/5283 ,  H01L21/4853 ,  H01L21/76885 ,  H01L21/82 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/522 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/82 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48464 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73267 ,  H01L2224/78 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2224/85909 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

摘要翻译： 包括用于形成这种互连结构的互连结构和方法的封装半导体组件在本文中公开。 封装半导体组件的一个实施例包括具有第一结合位置的支撑构件和由具有第二结合位点的支撑构件承载的模具。 互连结构连接在第一和第二结合位点之间，并且包括耦合到第一和第二键合位置中的至少一个的导线。 互连结构还包括在第一和第二键合位点之间耦合到线的第三键位置。

公开(公告)号：US08525320B2

公开(公告)日：2013-09-03

申请号：US13110060

申请日：2011-05-18

申请人： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon ,  Wuu Yean Tay

发明人： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon ,  Wuu Yean Tay

IPC分类号： H01L23/02

CPC分类号： H01L23/49527 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2924/01078

摘要： Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads.

摘要翻译： 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，一种制造微电子器件的方法包括将具有第一介电壳体的第一管芯封装堆叠在具有第二介电壳体的第二管芯封装的顶部上，使第一壳体的侧表面上的第一金属引线与第二金属 在第二壳体的第二侧表面处引导，并且形成将单独的第一引线连接到单独的第二引线的金属焊料连接器。 在另一个实施例中，制造微电子器件的方法还可以包括通过将金属焊料施加到第一侧表面的一部分，第二侧表面的一部分，以及跨越第一管芯封装和第二侧表面之间的间隙来形成连接器 第二管芯封装，使得连接器由金属焊料形成，其润湿到各个第一引线和各个第二引线。

公开(公告)号：US08445330B2

公开(公告)日：2013-05-21

申请号：US13459801

申请日：2012-04-30

申请人： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng

发明人： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng

IPC分类号： H01L21/00 ,  H01L23/48

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L23/49861 ,  H01L24/97 ,  H01L25/105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15331

摘要： Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a packaged semiconductor assembly includes a die attached to a support layer. A plurality of interconnects are embedded in and project from the support layer, such that the support layer at least partially retains the interconnects in a predetermined array. An encapsulant is molded around each of the interconnects and encases at least a portion of the die, support layer and interconnects.

摘要翻译： 封装的半导体器件和组件，包括用于形成这种互连的互连和方法。 封装半导体组件的一个实施例包括附接到支撑层的裸片。 多个互连嵌入在支撑层中并从支撑层突出，使得支撑层至少部分地将互连保持在预定的阵列中。 围绕每个互连件模制密封剂并且包封芯片，支撑层和互连件的至少一部分。

公开(公告)号：US07855462B2

公开(公告)日：2010-12-21

申请号：US11846928

申请日：2007-08-29

申请人： Suan Jeung Boon ,  Meow Koon Eng ,  Yong Poo Chia

发明人： Suan Jeung Boon ,  Meow Koon Eng ,  Yong Poo Chia

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5283 ,  H01L21/4853 ,  H01L21/76885 ,  H01L21/82 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/522 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/82 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48464 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73267 ,  H01L2224/78 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2224/85909 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

摘要翻译： 包括用于形成这种互连结构的互连结构和方法的封装半导体组件在本文中公开。 封装半导体组件的一个实施例包括具有第一结合位置的支撑构件和由具有第二结合位点的支撑构件承载的模具。 互连结构连接在第一和第二结合位点之间，并且包括耦合到第一和第二键合位置中的至少一个的导线。 互连结构还包括在第一和第二键合位点之间耦合到线的第三键位置。

公开(公告)号：US07791203B2

公开(公告)日：2010-09-07

申请号：US11848836

申请日：2007-08-31

申请人： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng

发明人： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng

IPC分类号： H01L23/48

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L23/49861 ,  H01L24/97 ,  H01L25/105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15331

摘要： Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a packaged semiconductor assembly includes a die attached to a support layer. A plurality of interconnects are embedded in and project from the support layer, such that the support layer at least partially retains the interconnects in a predetermined array. An encapsulant is molded around each of the interconnects and encases at least a portion of the die, support layer and interconnects.

摘要翻译： 封装的半导体器件和组件，包括用于形成这种互连的互连和方法。 封装半导体组件的一个实施例包括附接到支撑层的裸片。 多个互连嵌入在支撑层中并从支撑层突出，使得支撑层至少部分地将互连保持在预定的阵列中。 围绕每个互连件模制密封剂并且包封芯片，支撑层和互连件的至少一部分。

公开(公告)号：US07659134B2

公开(公告)日：2010-02-09

申请号：US11849062

申请日：2007-08-31

申请人： Yong Poo Chia ,  Yong Loo Neo ,  Meow Koon Eng

发明人： Yong Poo Chia ,  Yong Loo Neo ,  Meow Koon Eng

IPC分类号： H01L21/00

CPC分类号： H01L27/14683 ,  H01L27/14618 ,  H01L31/0203 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/05599

摘要： Microelectronic imagers and methods of manufacturing such microelectronic imagers are disclosed. In one embodiment, a method for manufacturing a microelectronic imager can include irradiating selected portions of an imager housing unit. The housing unit includes a body having lead-in surfaces and a support surface that define a recess sized to receive a microelectronic die. The method also includes depositing a conductive material onto the irradiated portions of the housing unit and forming electrically conductive traces. The method further includes coupling a plurality of terminals at a front side of a microelectronic die to corresponding electrically conductive traces in the recess in a flip-chip configuration. The microelectronic die includes an image sensor aligned with at least a portion of an optical element carried by the housing unit and at least partially aligned with the recess. The method can then include depositing an encapsulant into the recess and over at least a portion of the microelectronic die.

摘要翻译： 公开了微电子成像器和制造这种微电子成像器的方法。 在一个实施例中，用于制造微电子成像器的方法可以包括照射成像器壳体单元的选定部分。 壳体单元包括具有引入表面的本体和限定凹部的支撑表面，所述凹部的尺寸适于容纳微电子管芯。 该方法还包括将导电材料沉积到壳体单元的照射部分上并形成导电迹线。 该方法还包括将微电子管芯的前侧上的多个端子以倒装芯片配置耦合到凹槽中的对应导电迹线。 微电子管芯包括与由壳体单元承载并至少部分地与凹部对准的光学元件的至少一部分对准的图像传感器。 该方法然后可以包括将密封剂沉积到凹部中并在微电子管芯的至少一部分上方。

公开(公告)号：US20110215453A1

公开(公告)日：2011-09-08

申请号：US13110060

申请日：2011-05-18

申请人： Meow Koon Eng ,  Chia Yong Poo ,  Boon Suan Jeung ,  Tay Wuu Yean

发明人： Meow Koon Eng ,  Chia Yong Poo ,  Boon Suan Jeung ,  Tay Wuu Yean

IPC分类号： H01L25/11

CPC分类号： H01L23/49527 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2924/01078

摘要： Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads.

摘要翻译： 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，一种制造微电子器件的方法包括将具有第一介电壳体的第一管芯封装堆叠在具有第二介电壳体的第二管芯封装的顶部上，使第一壳体的侧表面上的第一金属引线与第二金属 在第二壳体的第二侧表面处引导，并且形成将单独的第一引线连接到单独的第二引线的金属焊料连接器。 在另一个实施例中，制造微电子器件的方法还可以包括通过将金属焊料施加到第一侧表面的一部分，第二侧表面的一部分，以及跨越第一管芯封装和第二侧表面之间的间隙来形成连接器 第二管芯封装，使得连接器由金属焊料形成，其润湿到各个第一引线和各个第二引线。