公开(公告)号：US08525320B2

公开(公告)日：2013-09-03

申请号：US13110060

申请日：2011-05-18

申请人： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon ,  Wuu Yean Tay

发明人： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon ,  Wuu Yean Tay

IPC分类号： H01L23/02

CPC分类号： H01L23/49527 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2924/01078

摘要： Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads.

摘要翻译： 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，一种制造微电子器件的方法包括将具有第一介电壳体的第一管芯封装堆叠在具有第二介电壳体的第二管芯封装的顶部上，使第一壳体的侧表面上的第一金属引线与第二金属 在第二壳体的第二侧表面处引导，并且形成将单独的第一引线连接到单独的第二引线的金属焊料连接器。 在另一个实施例中，制造微电子器件的方法还可以包括通过将金属焊料施加到第一侧表面的一部分，第二侧表面的一部分，以及跨越第一管芯封装和第二侧表面之间的间隙来形成连接器 第二管芯封装，使得连接器由金属焊料形成，其润湿到各个第一引线和各个第二引线。

公开(公告)号：US06856155B2

公开(公告)日：2005-02-15

申请号：US10266140

申请日：2002-10-07

申请人： Wuu Yean Tay ,  Yong Kian Tan ,  Yong Poo Chia ,  Siu Waf Low ,  Suan Jeung Boon ,  Soon Huat Goh

发明人： Wuu Yean Tay ,  Yong Kian Tan ,  Yong Poo Chia ,  Siu Waf Low ,  Suan Jeung Boon ,  Soon Huat Goh

IPC分类号： G01R31/28 ,  G01R31/02

CPC分类号： G01R31/2863

摘要： A testing scheme for ball-grid array devices of different sizes where the same ball-grid pattern may be tested using the same set of test adapters. A testing scheme includes providing a plurality of devices having a predetermined pattern of solder balls attached, providing a plurality of adapters secured to a test board, each of the adapters including a plurality of test contacts arranged in a pattern corresponding to the predetermined pattern of solder balls, removably attaching the plurality of devices to a device holding apparatus such that the predetermined pattern of solder balls on the devices corresponds to the predetermined pattern of test contacts on the plurality of adapters, then positioning the device holding apparatus to bring the plurality of solder balls in contact with the plurality of test contacts.

摘要翻译： 不同尺寸的球栅阵列器件的测试方案，可以使用相同的一组测试适配器测试相同的球栅图案。 一种测试方案包括提供多个具有附着的焊球预定图案的装置，提供固定在测试板上的多个适配器，每个适配器包括以对应于预定图案焊料的图案布置的多个测试触点 球，可移除地将多个装置附接到装置保持装置，使得装置上的预定图案的焊球对应于多个适配器上的预定图案的试验接触，然后定位装置保持装置以使多个焊料 与多个测试触点接触的球。

公开(公告)号：US08232657B2

公开(公告)日：2012-07-31

申请号：US12973607

申请日：2010-12-20

申请人： Suan Jeung Boon ,  Meow Koon Eng ,  Yong Poo Chia

发明人： Suan Jeung Boon ,  Meow Koon Eng ,  Yong Poo Chia

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5283 ,  H01L21/4853 ,  H01L21/76885 ,  H01L21/82 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/522 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/82 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48464 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73267 ,  H01L2224/78 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2224/85909 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

摘要翻译： 包括用于形成这种互连结构的互连结构和方法的封装半导体组件在本文中公开。 封装半导体组件的一个实施例包括具有第一结合位置的支撑构件和由具有第二结合位点的支撑构件承载的模具。 互连结构连接在第一和第二结合位点之间，并且包括耦合到第一和第二键合位置中的至少一个的导线。 互连结构还包括在第一和第二键合位点之间耦合到线的第三键位置。

公开(公告)号：US20100072603A1

公开(公告)日：2010-03-25

申请号：US12627352

申请日：2009-11-30

申请人： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng ,  Siu Waf Low

发明人： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng ,  Siu Waf Low

IPC分类号： H01L23/498

CPC分类号： H01L21/568 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/97 ,  H01L25/105 ,  H01L2225/1058 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

摘要： A sacrificial substrate for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. A semiconductor device assembly or package includes a semiconductor device, a redistribution layer over an active surface of the semiconductor device, and dielectric material coating at least portions of an outer periphery of the semiconductor device. Peripheral sections of contacts are located on the peripheral edge and electrically isolated therefrom by the dielectric coating. The contacts may also include upper sections that extend partially over the active surface of the semiconductor device. The assembly or package may include any type of semiconductor device, including a processor, a memory device, and emitter, or an optically sensitive device.

摘要翻译： 用于制造具有边缘触点的半导体器件组件和封装的牺牲衬底包括其表面上的导电元件，其被定位成沿着设备衬底上的每个相邻的一对半导体器件之间的街道排列。 半导体器件组件或封装包括半导体器件，半导体器件的有源表面上的再分布层，以及涂覆半导体器件外周的至少部分的电介质材料。 触点的周边部分位于外围边缘，并通过电介质涂层与其隔离。 触点还可以包括在半导体器件的有效表面上部分延伸的上部部分。 组件或封装可以包括任何类型的半导体器件，包括处理器，存储器件和发射极，或光敏器件。

公开(公告)号：US07485562B2

公开(公告)日：2009-02-03

申请号：US11028374

申请日：2005-01-03

申请人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

发明人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2224/05599

摘要： The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up, wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice. Computing systems incorporating the packaging are also disclosed.

摘要翻译： 本发明定义了在芯片解决方案上提供多芯片多层系统的封装实现。 实现了包含在形成在单独基板中的空腔内的多个和多种已知的良好模具的更大整合。 在多芯片配置之上的附加再分布和互连层可以形成为具有终止于诸如导电凸块或球的电连接的再分布层。 在一个实施例中，衬底空腔以倒装芯片配置接收多个半导体晶片的信号器件连接，例如导电凸块。 然后将衬底的背面的一部分去除足以露出导电凸块的深度。 在另一个实施例中，空腔容纳半导体晶片，其有源表面朝上，其中形成金属层连接并耦合到半导体晶片的接合焊盘或其它电连接器。 还公开了包含包装的计算系统。

公开(公告)号：US07208335B2

公开(公告)日：2007-04-24

申请号：US10717421

申请日：2003-11-19

申请人： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng ,  Siu Waf Low

发明人： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng ,  Siu Waf Low

IPC分类号： H01L21/00 ,  H01L21/30

CPC分类号： H01L21/568 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/97 ,  H01L25/105 ,  H01L2225/1058 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

摘要： A method for fabricating a chip-scale package includes securing a device substrate that carries at least two adjacent semiconductor devices to a sacrificial substrate. The sacrificial substrate may include conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. The device substrate is then severed along each street and the newly formed peripheral edge of each semiconductor device coated with dielectric material. If the sacrificial substrate includes conductive elements, they may be exposed between adjacent semiconductor devices and subsequently serve as lower sections of contacts. Peripheral sections of contacts are formed on the peripheral edge. Upper sections of the contacts may also be formed over the active surfaces of the semiconductor devices. Once the contacts are formed, the sacrificial substrate is substantially removed from the back sides of the semiconductor devices.

摘要翻译： 一种用于制造芯片级封装件的方法包括将承载至少两个相邻半导体器件的器件衬底固定到牺牲衬底。 牺牲衬底可以包括在其表面上的导电元件，其位于沿着设备衬底上每个相邻的一对半导体器件之间的街道对齐。 然后沿着每个街道切割设备基板，并且每个半导体器件的新形成的外围边缘被涂覆有电介质材料。 如果牺牲衬底包括导电元件，则它们可以在相邻的半导体器件之间暴露，并且随后用作接触的下部。 触点的外围部分形成在周边。 触点的上部部分也可以形成在半导体器件的有效表面上。 一旦接触形成，牺牲基底基本上从半导体器件的背面去除。

公开(公告)号：US07193312B2

公开(公告)日：2007-03-20

申请号：US11222365

申请日：2005-09-07

申请人： Suan Jeung Boon ,  Yong Poo Chia ,  Siu Waf Low ,  Meow Koon Eng ,  Swee Kwang Chua ,  Shuang Wu Huang ,  Yong Loo Neo ,  Wei Zhou

发明人： Suan Jeung Boon ,  Yong Poo Chia ,  Siu Waf Low ,  Meow Koon Eng ,  Swee Kwang Chua ,  Shuang Wu Huang ,  Yong Loo Neo ,  Wei Zhou

IPC分类号： H01L23/48

CPC分类号： H01L25/50 ,  H01L23/3114 ,  H01L23/49805 ,  H01L24/05 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/73267 ,  H01L2224/85399 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

摘要： Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

公开(公告)号：US06964881B2

公开(公告)日：2005-11-15

申请号：US10229914

申请日：2002-08-27

申请人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

发明人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

IPC分类号： H01L21/60 ,  H01L23/498 ,  H01L23/538 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/4763

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2224/05599

摘要： The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die are contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with the active surface of the semiconductor dice facing up, wherein metal layer connections are formed and coupled bond pads or other electrical connectors of the semiconductor dice.

摘要翻译： 本发明定义了在芯片解决方案上提供多芯片多层系统的封装实现。 实现了包含在形成在单独基板中的空腔内的多个和多种已知的良好模具的更大整合。 在多芯片配置之上的附加再分布和互连层可以形成为具有终止于诸如导电凸块或球的电连接的再分布层。 在一个实施例中，衬底的空腔以倒装芯片配置接收多个半导体晶片的信号器件连接，例如导电凸块。 然后将衬底背面的一部分去除足以露出导电凸块的深度。 在另一个实施例中，空腔接收半导体晶片，其中半导体晶片的有源表面朝上，其中形成金属层连接并耦合到半导体晶片的接合焊盘或其它电连接器。

公开(公告)号：US08536702B2

公开(公告)日：2013-09-17

申请号：US13492554

申请日：2012-06-08

申请人： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon

发明人： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon

IPC分类号： H01L23/48

CPC分类号： H01L25/105 ,  H01L21/50 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49555 ,  H01L23/49811 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/17 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16258 ,  H01L2224/17106 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

摘要： Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.

摘要翻译： 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，堆叠封装的系统包括具有底侧的第一裸片封装，第一电介质外壳和第一金属引线; 具有附接到第一封装的底侧的顶侧的第二管芯封装，具有侧面的电介质外壳和与第一金属引线对准并朝向第一金属引线突出的第二金属引线，并且包括外表面和内表面区域， 一般面向外侧; 和金属焊接连接器将各个第一引线连接到单独的第二引线。 在另一个实施例中，各个第二引线具有“L”形状并且物理地接触相应的单个第一引线。 在另一个实施例中，各个第二引线具有“C”形并且包括向第二壳体的侧面突出的分层部分。

公开(公告)号：US08198720B2

公开(公告)日：2012-06-12

申请号：US12955666

申请日：2010-11-29

申请人： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon

发明人： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon

IPC分类号： H01L25/065

CPC分类号： H01L25/105 ,  H01L21/50 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49555 ,  H01L23/49811 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/17 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16258 ,  H01L2224/17106 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

摘要： Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.

摘要翻译： 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，堆叠封装的系统包括具有底侧的第一裸片封装，第一电介质外壳和第一金属引线; 第二管芯封装，其具有附接到第一封装的底侧的顶侧，具有侧面的电介质外壳和与第一金属引线对准并朝向第一金属引线突出的第二金属引线，并且包括外表面和内表面区域， 一般面向外侧; 和金属焊接连接器将各个第一引线连接到单独的第二引线。 在另一个实施例中，各个第二引线具有“L”形状并且物理地接触相应的单个第一引线。 在另一个实施例中，各个第二引线具有“C”形并且包括向第二壳体的侧面突出的分层部分。