公开(公告)号：US20110084402A1

公开(公告)日：2011-04-14

申请号：US12973607

申请日：2010-12-20

Applicant: Boon Suan Jeung ,  Eng Meow Koon ,  Chia Yong Poo

Inventor： Boon Suan Jeung ,  Eng Meow Koon ,  Chia Yong Poo

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/56 ,  H01L21/50

CPC classification number: H01L23/5283 ,  H01L21/4853 ,  H01L21/76885 ,  H01L21/82 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/522 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/82 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48464 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73267 ,  H01L2224/78 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2224/85909 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

Abstract translation: 包括用于形成这种互连结构的互连结构和方法的封装半导体组件在本文中公开。 封装半导体组件的一个实施例包括具有第一结合位置的支撑构件和由具有第二结合位点的支撑构件承载的模具。 互连结构连接在第一和第二结合位点之间，并且包括耦合到第一和第二键合位置中的至少一个的导线。 互连结构还包括在第一和第二键合位点之间耦合到线的第三键位置。

公开(公告)号：US20110068454A1

公开(公告)日：2011-03-24

申请号：US12955666

申请日：2010-11-29

Applicant: Eng Meow Koon ,  Chia Yong Poo ,  Boon Suan Jeung

Inventor： Eng Meow Koon ,  Chia Yong Poo ,  Boon Suan Jeung

IPC: H01L25/065

CPC classification number: H01L25/105 ,  H01L21/50 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49555 ,  H01L23/49811 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/17 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16258 ,  H01L2224/17106 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.

Abstract translation: 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，堆叠封装的系统包括具有底侧的第一裸片封装，第一电介质外壳和第一金属引线; 具有附接到第一封装的底侧的顶侧的第二管芯封装，具有侧面的电介质外壳和与第一金属引线对准并朝向第一金属引线突出的第二金属引线，并且包括外表面和内表面区域， 一般面向外侧; 和金属焊接连接器将各个第一引线连接到单独的第二引线。 在另一个实施例中，各个第二引线具有“L”形状并且物理地接触相应的单个第一引线。 在另一个实施例中，各个第二引线具有“C”形并且包括向第二壳体的侧面突出的分层部分。

公开(公告)号：US20090014859A1

公开(公告)日：2009-01-15

申请号：US11848836

申请日：2007-08-31

Applicant: Boon Suan Jeung ,  Chia Yong Poo ,  Eng Meow Koon

Inventor： Boon Suan Jeung ,  Chia Yong Poo ,  Eng Meow Koon

IPC: H01L23/12 ,  H01L21/56 ,  H01L23/48

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L23/49861 ,  H01L24/97 ,  H01L25/105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15331

Abstract: Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a packaged semiconductor assembly includes a die attached to a support layer. A plurality of interconnects are embedded in and project from the support layer, such that the support layer at least partially retains the interconnects in a predetermined array. An encapsulant is molded around each of the interconnects and encases at least a portion of the die, support layer and interconnects.

Abstract translation: 封装的半导体器件和组件，包括用于形成这种互连的互连和方法。 封装半导体组件的一个实施例包括附接到支撑层的裸片。 多个互连嵌入在支撑层中并从支撑层突出，使得支撑层至少部分地将互连保持在预定的阵列中。 围绕每个互连件模制密封剂并且包封芯片，支撑层和互连件的至少一部分。

公开(公告)号：US20090014822A1

公开(公告)日：2009-01-15

申请号：US11849062

申请日：2007-08-31

Applicant: Chia Yong Poo ,  Neo Yong Loo ,  Eng Meow Koon

Inventor： Chia Yong Poo ,  Neo Yong Loo ,  Eng Meow Koon

IPC: H01L31/0232 ,  H01L31/18

CPC classification number: H01L27/14683 ,  H01L27/14618 ,  H01L31/0203 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/05599

Abstract: Microelectronic imagers and methods of manufacturing such microelectronic imagers are disclosed. In one embodiment, a method for manufacturing a microelectronic imager can include irradiating selected portions of an imager housing unit. The housing unit includes a body having lead-in surfaces and a support surface that define a recess sized to receive a microelectronic die. The method also includes depositing a conductive material onto the irradiated portions of the housing unit and forming electrically conductive traces. The method further includes coupling a plurality of terminals at a front side of a microelectronic die to corresponding electrically conductive traces in the recess in a flip-chip configuration. The microelectronic die includes an image sensor aligned with at least a portion of an optical element carried by the housing unit and at least partially aligned with the recess. The method can then include depositing an encapsulant into the recess and over at least a portion of the microelectronic die.

Abstract translation: 公开了微电子成像器和制造这种微电子成像器的方法。 在一个实施例中，用于制造微电子成像器的方法可以包括照射成像器壳体单元的选定部分。 壳体单元包括具有引入表面的本体和限定凹部的支撑表面，所述凹部的尺寸适于容纳微电子管芯。 该方法还包括将导电材料沉积到壳体单元的照射部分上并形成导电迹线。 该方法还包括将微电子管芯的前侧上的多个端子以倒装芯片配置耦合到凹槽中的对应导电迹线。 微电子管芯包括与由壳体单元承载并至少部分地与凹部对准的光学元件的至少一部分对准的图像传感器。 该方法然后可以包括将密封剂沉积到凹部中并在微电子管芯的至少一部分上方。

公开(公告)号：US07276387B2

公开(公告)日：2007-10-02

申请号：US11221521

申请日：2005-09-07

Applicant: Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf ,  Eng Meow Koon ,  Chua Swee Kwang ,  Huang Shuang Wu ,  Neo Yong Loo ,  Zhou Wei

Inventor： Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf ,  Eng Meow Koon ,  Chua Swee Kwang ,  Huang Shuang Wu ,  Neo Yong Loo ,  Zhou Wei

IPC: H01L21/66 ,  H01L21/00

CPC classification number: H01L25/50 ,  H01L23/3114 ,  H01L23/49805 ,  H01L24/05 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/73267 ,  H01L2224/85399 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

公开(公告)号：US07115984B2

公开(公告)日：2006-10-03

申请号：US10736244

申请日：2003-12-15

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Chua Swee Kwang

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Chua Swee Kwang

IPC: H01L23/02 ,  H01L23/48

CPC classification number: H01L23/49838 ,  H01L23/49805 ,  H01L25/105 ,  H01L2225/1064 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15312 ,  H01L2924/00

Abstract: A semiconductor device package is disclosed which is substantially die-sized with respect to each of the X, Y and Z axes. The package includes outer connectors that are located along at least one peripheral edge thereof and that extend substantially across the height of the peripheral edge. Each outer connector is formed by severing a conductive via that extends substantially through a substrate blank, such as a silicon wafer, at a street located adjacent to an outer periphery of the semiconductor device of the package. The outer connectors may include recesses that at least partially receive conductive columns protruding from a support substrate therefor. Assemblies may include the packages in stacked arrangement, without height-adding connectors.

Abstract translation: 公开了一种相对于X，Y和Z轴中的每一个基本上模具尺寸的半导体器件封装。 该包装件包括沿其至少一个周边边缘定位的外部连接器，并且基本上横跨周边边缘的高度延伸。 每个外部连接器通过在位于与封装的半导体器件的外周相邻的街道处切断基本上穿过基板坯料（例如硅晶片）的导电通孔来形成。 外部连接器可以包括至少部分地接收从支撑基板突出的导电柱的凹部。 组件可以包括堆叠布置的封装，而不增加高度的连接器。

公开(公告)号：US06790706B2

公开(公告)日：2004-09-14

申请号：US10285136

申请日：2002-10-30

Applicant: Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf

Inventor： Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf

IPC: H01L2144

CPC classification number: H01L25/50 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48472 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2224/85399 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/07025 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention is directed to a leadless and interconnected semiconductor package. The package includes a first chip having bond pads with a second chip having bond pads positioned on the first chip to form a vertically stacked package. Interconnections between the bond pads are formed by metallized layers on the package that extend to an edge of the package to join castellations along sides of the package to form a plurality of leadless input/output locations for the package. In one embodiment, the castellations include planar metallized portions. In another embodiment, the castellations include semi-cylindrical metallized portions. In still another embodiment, insulators are positioned between the chips, and on the package base. In still another embodiment, a chip includes a photosensitive device having screening optical layers. Bond pads on the chip are electrically coupled to castellations extending from the bond pads to form leadless input/output locations for the package.

公开(公告)号：US06582992B2

公开(公告)日：2003-06-24

申请号：US10222294

申请日：2002-08-15

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Chua Swee Kwang

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Chua Swee Kwang

IPC: H01L2144

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06586 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/07811 ,  H01L2924/00

Abstract: A stackable semiconductor package includes a semiconductor die, and has a chip sized peripheral outline matching that of the die. In addition to the die, the package includes stacking pads and stacking contacts on opposing sides of the die, and conductive grooves on the edges of the die in electrical communication with the stacking pads and the stacking contacts. The conductive grooves function as interlevel conductors for the package and can also function as edge contacts for the package. The configuration of the stacking pads, of the stacking contacts and of the conductive grooves permit multiple packages to be stacked and electrically interconnected to form stacked assemblies. A method for fabricating the package is performed at the wafer level on a substrate, such as a semiconductor wafer, containing multiple dice. In addition, multiple substrates can be stacked, bonded and singulated to form stacked assemblies that include multiple stacked packages.

Abstract translation: 可堆叠的半导体封装包括半导体管芯，并且具有与管芯相匹配的芯片尺寸的外围轮廓。 除了管芯之外，封装还包括在管芯的相对侧上的堆叠焊盘和堆叠触点，以及与堆叠焊盘和堆叠触点电连通的管芯边缘上的导电槽。 导电槽用作封装的层间导体，并且还可以用作封装的边缘触点。 堆叠焊盘，堆叠触点和导电沟槽的配置允许多个封装堆叠并电互连以形成堆叠的组件。 用于制造封装的方法在晶片级上在诸如半导体晶片的基板上进行，该半导体晶片包含多个管芯。 此外，可以堆叠，粘合和分割多个基板以形成包括多个堆叠封装的堆叠组件。

公开(公告)号：US20120241982A1

公开(公告)日：2012-09-27

申请号：US13441533

申请日：2012-04-06

Applicant: Boon Suan Jeung ,  Eng Meow Koon ,  Chia Yong Poo

Inventor： Boon Suan Jeung ,  Eng Meow Koon ,  Chia Yong Poo

IPC: H01L25/03 ,  H01L21/60

CPC classification number: H01L23/5283 ,  H01L21/4853 ,  H01L21/76885 ,  H01L21/82 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/522 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/82 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48464 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73267 ,  H01L2224/78 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2224/85909 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

Abstract translation: 包括用于形成这种互连结构的互连结构和方法的封装半导体组件在本文中公开。 封装半导体组件的一个实施例包括具有第一结合位置的支撑构件和由具有第二结合位点的支撑构件承载的模具。 互连结构连接在第一和第二结合位点之间，并且包括耦合到第一和第二键合位置中的至少一个的导线。 互连结构还包括在第一和第二键合位点之间耦合到线的第三键位置。

公开(公告)号：US20120241957A1

公开(公告)日：2012-09-27

申请号：US13492554

申请日：2012-06-08

Applicant: Eng Meow Koon ,  Chia Yong Poo ,  Boon Suan Jeung

Inventor： Eng Meow Koon ,  Chia Yong Poo ,  Boon Suan Jeung

IPC: H01L23/48

CPC classification number: H01L25/105 ,  H01L21/50 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49555 ,  H01L23/49811 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/17 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16258 ,  H01L2224/17106 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.

Abstract translation: 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，堆叠封装的系统包括具有底侧的第一裸片封装，第一电介质外壳和第一金属引线; 第二管芯封装，其具有附接到第一封装的底侧的顶侧，具有侧面的电介质外壳和与第一金属引线对准并朝向第一金属引线突出的第二金属引线，并且包括外表面和内表面区域， 一般面向外侧; 和金属焊接连接器将各个第一引线连接到单独的第二引线。 在另一个实施例中，各个第二引线具有“L”形状并且物理地接触相应的单个第一引线。 在另一个实施例中，各个第二引线具有“C”形并且包括向第二壳体的侧面突出的分层部分。