公开(公告)号：US11335614B2

公开(公告)日：2022-05-17

申请号：US16754395

申请日：2018-10-25

Applicant: TDK CORPORATION

Inventor： Takaaki Morita ,  Kenichi Yoshida ,  Mitsuhiro Tomikawa

IPC: H05K1/18 ,  H01L23/12 ,  H01L23/498 ,  H01L23/00

Abstract: In an electric component embedded structure, a first electrode terminal provided on a first main surface includes an intra-area terminal, and the intra-area terminal is electrically connected to an overlap portion of an overlap wiring in a formation area of an electric component. Accordingly, a decrease in mounting area of the electric component embedded structure is achieved. The intra-area terminal can be electrically connected to a second electrode terminal provided on a second main surface via a first via-conductor, the overlap wiring, and a second via-conductor. The intra-area terminal is connected to a wiring (an overlap wiring) of a first insulating layer without additionally providing a rewiring layer causing an increase in thickness, and the increase in thickness is curbed, whereby a decrease in size of the electric component embedded structure is achieved.

公开(公告)号：US11276531B2

公开(公告)日：2022-03-15

申请号：US16617106

申请日：2018-05-16

Applicant: TDK Corporation

Inventor： Koichi Tsunoda ,  Kazuhiro Yoshikawa ,  Mitsuhiro Tomikawa ,  Kenichi Yoshida

IPC: H01G4/33 ,  H01G4/01 ,  H01G4/232

Abstract: A thin-film capacitor includes an insulating base member, and a capacitance portion that is laminated on the insulating base member has a plurality of internal electrode layers which are laminated on the insulating base member and are provided in a lamination direction and dielectric layers which are sandwiched between the internal electrode layers. A relative dielectric constant of the dielectric layers is 100 or higher.

公开(公告)号：US10483345B2

公开(公告)日：2019-11-19

申请号：US15891637

申请日：2018-02-08

Applicant: TDK CORPORATION

Inventor： Mitsuhiro Tomikawa ,  Koichi Tsunoda ,  Kazuhiro Yoshikawa ,  Kenichi Yoshida

IPC: H01G4/33 ,  H01G4/228 ,  H01L49/02 ,  H01G4/30

Abstract: An electronic component embedded substrate includes: a substrate that includes an insulating layer and has a first principal surface and a second principal surface on the opposite side of the first principal surface; and an electronic component that is embedded in the substrate and has a plurality of first terminals provided close to the first principal surface, a plurality of second terminals provided close to the second principal surface, and a capacity part provided between the plurality of first terminals and the plurality of second terminals. The electronic component is configured such that at least a part of the second terminals is embedded in the insulating layer. An insulating member is provided between the neighboring second terminals to be in contact with both of the neighboring second terminals. The insulating member and the insulating layer are formed of materials whose thermal expansion coefficients are different from each other.

公开(公告)号：US10392704B2

公开(公告)日：2019-08-27

申请号：US15415493

申请日：2017-01-25

Applicant: TDK CORPORATION

Inventor： Kenichi Yoshida ,  Yuhei Horikawa ,  Atsushi Sato ,  Hisayuki Abe

IPC: C23C18/42 ,  C23C18/16 ,  C23C18/32 ,  C23C18/54 ,  C23C28/02 ,  H01L23/00

Abstract: A method of providing a coating on a conductor. The coating has a first layer containing palladium and a second layer containing gold from the conductor side. The first layer has an inner layer on the conductor side and an outer layer arranged nearer to the second layer than the inner layer, and the outer layer has a higher phosphorus concentration than the inner layer.

公开(公告)号：US10278290B2

公开(公告)日：2019-04-30

申请号：US15654281

申请日：2017-07-19

Applicant: TDK CORPORATION

Inventor： Kenichi Yoshida ,  Mitsuhiro Tomikawa

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H01L23/00 ,  H01L23/538

Abstract: An electronic component embedded substrate 1 includes a substrate 10 having a wiring layer 11 and an insulating layer 12; an electronic component 20 built in the substrate 10, and having a pair of electrode layers 21A and 21B, and a dielectric layer 22; and a stress relieving layer 30 provided closer to the wiring layer 11 than the insulating layer 12 is in the lamination direction, wherein at least part of an end portion of the electronic component 20 on the wiring layer 11 side is in contact with the stress relieving layer 30, wherein at least part of an end portion of the electronic component 20 on the insulating layer 12 side is in contact with the insulating layer 12, and wherein the Young's modulus of the stress relieving layer 30 is lower than the Young's modulus of the electrode layer 21B.

公开(公告)号：US10211157B2

公开(公告)日：2019-02-19

申请号：US15633013

申请日：2017-06-26

Applicant: TDK CORPORATION

Inventor： Kenichi Yoshida ,  Mitsuhiro Tomikawa ,  Eiko Wakata

IPC: H01L23/538 ,  H01G4/005 ,  H01G4/228 ,  H05K1/16 ,  H01G4/33 ,  H01G4/40 ,  H01G4/232

Abstract: An electronic component includes a first electronic component and a second electronic component that is stacked on the first electronic component. A second electrode layer of the first electronic component includes a plurality of divided electrode layers, and a pair of electrodes of the second electronic component are electrically connected to different electrode layers included in the plurality of electrode layers of the second electrode layer, and a first electrode layer of the first electronic component is divided into a plurality of electrode layers to correspond to the electrode layers which are included in the second electrode layer and which are electrically connected to the pair of electrodes of the second electronic component.

公开(公告)号：US09640500B2

公开(公告)日：2017-05-02

申请号：US13960173

申请日：2013-08-06

Applicant: TDK CORPORATION

Inventor： Kenichi Yoshida ,  Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: The present invention relates to a terminal structure comprising; a base material 10; an external electrode 20 formed on the base material; an insulating coating layer 30 formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under-bump metal layer 70 filling the opening and covering part of the insulating coating layer; and a dome-shaped bump 85 covering the under-bump metal layer, wherein in a cross section along a lamination direction, the under-bump metal layer has a convex shape toward the bump, and the thickness Tu0 of the under-bump metal layer at a center of the opening is equal to or greater than the thickness Tu1 of the under-bump metal layer at an end portion of the opening.

公开(公告)号：US09070606B2

公开(公告)日：2015-06-30

申请号：US13960228

申请日：2013-08-06

Applicant: TDK CORPORATION

Inventor： Kenichi Yoshida ,  Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L23/485 ,  H01L23/492 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2224/05552

Abstract: The present invention relates to a terminal structure comprising: a base material 10; an external electrode 20 formed on the base material; an insulating coating layer 30 formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under-bump metal layer 70 filling the opening and covering part of the insulating coating layer; and a dome-shaped bump 85 covering the under-bump metal layer, wherein in a cross section along a lamination direction, a height Hbm at which the bump has a maximum diameter (Lbm) is lower than a maximum height Hu of the under-bump metal layer.

Abstract translation: 本发明涉及一种端子结构，包括：基材10; 形成在基材上的外部电极20; 绝缘涂层30，形成在基材和电极上，并具有露出电极的至少一部分的开口; 填充绝缘涂层的开口和覆盖部分的凸块下金属层70; 以及覆盖凸块下金属层的圆顶状凸起85，其中在沿着层叠方向的截面中，所述凸块具有最大直径（Lbm）的高度Hbm低于所述凸块下凸块的最大高度Hu， 凸块金属层。

公开(公告)号：US08976076B2

公开(公告)日：2015-03-10

申请号：US13790803

申请日：2013-03-08

Applicant: TDK Corporation

Inventor： Kenichi Yoshida ,  Yuhei Horikawa

IPC: H01Q1/36 ,  H01P3/08 ,  H01Q1/50 ,  H01P11/00

CPC classification number: H01P3/08 ,  H01P11/003 ,  H01Q1/36 ,  H01Q1/50

Abstract: A high-frequency transmission line having low alternate current (AC) resistance is provided. One aspect of the present invention is a high-frequency transmission line disposed along a surface of an insulating support, wherein, letting F [Hz] be the frequency of an AC electric signal transmitted by the high-frequency transmission line and Ms [Wb/m] be the saturation magnetization per unit area, the frequency value F and the saturation magnification value per unit area Ms satisfy the following expression (1): Ms≦(1.5×102)/F+5.7×10−8  (1).

Abstract translation: 提供具有低交流（AC）电阻的高频传输线。 本发明的一个方面是沿着绝缘支撑体的表面布置的高频传输线，其中，使F [Hz]为由高频传输线发送的AC电信号的频率，Ms [Wb / m]为每单位面积的饱和磁化强度，每单位面积Ms的频率值F和饱和倍率值满足下式（1）：Ms＆nlE;（1.5×102）/ F +5.7×10-8（1）。

公开(公告)号：US12237366B2

公开(公告)日：2025-02-25

申请号：US18012820

申请日：2020-12-24

Applicant: TDK Corporation

Inventor： Daiki Ishii ,  Yoshihiko Yano ,  Yuki Yamashita ,  Kenichi Yoshida ,  Tetsuhiro Takahashi

IPC: H01G4/005 ,  H01G2/06 ,  H01G4/008 ,  H01G4/01 ,  H01G4/012 ,  H01G4/06 ,  H01G4/10 ,  H01G4/12 ,  H01G4/228 ,  H01G4/33 ,  H01L25/16 ,  H01L49/02 ,  H05K1/18 ,  H01G4/252 ,  H01L23/00

Abstract: To provide a thin film capacitor having high adhesion with respect to a circuit substrate. A thin film capacitor includes: a metal foil having a roughened upper surface; a dielectric film covering the upper surface of the metal foil and having an opening through which the metal foil is partly exposed; a first electrode layer contacting the metal foil through the opening; and a second electrode layer contacting the dielectric film without contacting the metal foil. An angle θa formed by the other main surface of the metal foil and a side surface thereof is more than 20° and less than 80°. The side surface is thus tapered at an angle of more than 20° and less than 80°, so that it is possible to suppress warpage and to enhance adhesion with respect to a multilayer substrate when the thin film capacitor is embedded in the multilayer substrate.