公开(公告)号：US20190259717A1

公开(公告)日：2019-08-22

申请号：US15901631

申请日：2018-02-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/00 ,  H01L21/78

Abstract: A packaged semiconductor die includes a semiconductor die coupled to a die pad. The semiconductor die has a front side containing copper leads, a copper seed layer coupled to the copper leads, and a nickel alloy coating coupled to the copper seed layer. The nickel alloy includes tungsten and cerium (NiWCe). The packaged semiconductor die may also include wire bonds coupled between leads of a lead frame and the copper leads of the semiconductor die. In addition, the packaged semiconductor die may be encapsulated in molding compound. A method for fabricating a packaged semiconductor die. The method includes forming a copper seed layer over the copper leads of the semiconductor die. In addition, the method includes coating the copper seed layer with a nickel alloy. The method also includes singulating the semiconductor wafer to create individual semiconductor die and placing the semiconductor die onto a die pad of a lead frame. In addition the method includes wire bonding the leads of a lead frame to the copper leads of the semiconductor die and then encapsulating the die in molding compound.

公开(公告)号：US20190109074A1

公开(公告)日：2019-04-11

申请号：US15984343

申请日：2018-05-19

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Frank Pavone

IPC: H01L23/495 ,  H01L23/532 ,  H01L23/49 ,  H01L23/492 ,  H01L23/00

Abstract: A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed.

公开(公告)号：US20170117238A1

公开(公告)日：2017-04-27

申请号：US14923123

申请日：2015-10-26

Applicant: Texas Instruments Incorporated

Inventor： Matthew David Romig ,  Christopher Daniel Manack

IPC: H01L23/58 ,  H01L21/50

CPC classification number: H01L23/58 ,  H01L21/50 ,  H01L24/06 ,  H01L24/20 ,  H01L24/37 ,  H01L24/40 ,  H01L24/84 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40225 ,  H01L2224/40235 ,  H01L2224/84801 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00014

Abstract: An integrated power package includes a substrate having a first surface and an integrated circuit located within the substrate. At least one electrical conductor is located between the first surface and another point on the substrate. At least one transistor is electrically and mechanically coupled to the at least one first conductor. A support structure is electrically and mechanically coupled to the at least one transistor, wherein the at least one transistor is located between the first surface of the substrate and the support structure.

公开(公告)号：US20150004739A1

公开(公告)日：2015-01-01

申请号：US14490924

申请日：2014-09-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Daniel Manack ,  Frank Stepniak ,  Sreenivasan K. Koduri

IPC: B81C1/00

CPC classification number: B81C1/00246 ,  B81B7/0067 ,  B81B2201/0207 ,  B81C1/00269 ,  G01J5/045 ,  G01J5/12 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24245 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82

Abstract: A method for fabricating a micro-electro-mechanical system (MEMS) provides a semiconductor chip having a cavity with a radiation sensor MEMS. The opening of the cavity at the chip surface is covered by a plate transmissive to the radiation sensed by the MEMS. A patterned metal film is placed across the plate surface remote from the cavity.

Abstract translation: 微机电系统（MEMS）的制造方法提供具有辐射传感器MEMS的空腔的半导体芯片。 在芯片表面处的空腔的开口由对MEMS感测的辐射透射的板覆盖。 图案化的金属膜跨过位于空腔的板表面。

公开(公告)号：US12100678B2

公开(公告)日：2024-09-24

申请号：US16669070

申请日：2019-10-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Daniel Manack ,  Salvatore Frank Pavone ,  Maricel Fabia Escaño ,  Rafael Jose Lizares Guevara

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/81815

Abstract: In examples, a semiconductor package comprises a semiconductor die having an active surface; a conductive layer coupled to the active surface; and a polyimide layer coupled to the conductive layer. The package also comprises a conductive pillar coupled to the conductive layer and to the polyimide layer; a flux adhesive material coupled to the conductive pillar; and a solder layer coupled to the flux adhesive material. The package further includes a conductive terminal coupled to the solder layer and exposed to a surface of the package, the active surface of the semiconductor die facing the conductive terminal.

公开(公告)号：US11984418B2

公开(公告)日：2024-05-14

申请号：US17884284

申请日：2022-08-09

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Frank Pavone ,  Patrick Francis Thompson

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02317 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03502 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05618 ,  H01L2224/05647 ,  H01L2224/11424 ,  H01L2224/1145 ,  H01L2224/11848 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13618 ,  H01L2224/13647 ,  H01L2924/0132

Abstract: A method for manufacturing a package includes positioning a copper layer above a die. A zinc layer is positioned on the copper layer. The zinc and copper layers are then heated to produce a brass layer, the brass layer abutting the copper layer. Further, a polymer layer is positioned abutting the brass layer.

公开(公告)号：US11594504B2

公开(公告)日：2023-02-28

申请号：US17234429

申请日：2021-04-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/00 ,  H01L21/78

Abstract: A packaged semiconductor die includes a semiconductor die coupled to a die pad. The semiconductor die has a front side containing copper leads, a copper seed layer coupled to the copper leads, and a nickel alloy coating coupled to the copper seed layer. The nickel alloy includes tungsten and cerium (NiWCe). The packaged semiconductor die may also include wire bonds coupled between leads of a lead frame and the copper leads of the semiconductor die. In addition, the packaged semiconductor die may be encapsulated in molding compound. A method for fabricating a packaged semiconductor die. The method includes forming a copper seed layer over the copper leads of the semiconductor die. In addition, the method includes coating the copper seed layer with a nickel alloy. The method also includes singulating the semiconductor wafer to create individual semiconductor die and placing the semiconductor die onto a die pad of a lead frame.

公开(公告)号：US20220208655A1

公开(公告)日：2022-06-30

申请号：US17135700

申请日：2020-12-28

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Sreenivasan Kalyani Koduri

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions; at least one semiconductor device die over the die mount portion of the package substrate, the semiconductor device die having bond pads on an active surface facing away from the package substrate; electrical connections between at least one of the bond pads and one of the lead portions; a post interconnect over at least one of the bond pads, the post interconnect extending away from the active surface of the semiconductor device die; and a dielectric material covering a portion of the package substrate, the semiconductor device die, a portion of the post interconnect, and the electrical connections, forming a packaged semiconductor device, wherein the post interconnect extends through the dielectric material and had an end facing away from the semiconductor device die that is exposed from the dielectric material.

公开(公告)号：US11362047B2

公开(公告)日：2022-06-14

申请号：US16850620

申请日：2020-04-16

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC: H01L23/60 ,  H01L23/495 ,  H01L23/00 ,  H01L33/00 ,  H01L33/62 ,  H01L21/683

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

公开(公告)号：US20220157698A1

公开(公告)日：2022-05-19

申请号：US17098930

申请日：2020-11-16

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Jonathan Andrew Montoya ,  Jovenic Romero Esquejo ,  Salvatore Frank Pavone

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/50 ,  H01L21/768

Abstract: A semiconductor package includes an IC having circuitry configured for at least one function with some nodes connected to bond pads, with first metal posts on the bond pads, and dome support metal posts configured in a ring having a top rim defining an inner cavity with solder on the top rim and extending over an area of the inner cavity for providing a solder dome that covers the inner cavity to provide a covered air cavity over a portion of the circuitry. A leadframe includes a plurality of leads or lead terminals. The IC is flipchip attached with a solder connection to the leadframe so that the first metal posts are attached to the leads or the lead terminals. A mold compound provides encapsulation for the semiconductor package except on at least a bottom side of the leads or lead terminals.