公开(公告)号：US20140143486A1

公开(公告)日：2014-05-22

申请号：US14061470

申请日：2013-10-23

Applicant: Texas Instruments Incorporated

Inventor： Kai Chirca ,  Matthew D. Pierson

IPC: G06F3/06

CPC classification number: G06F12/084 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0683 ,  G06F11/1064 ,  G06F13/1652 ,  G06F13/1668 ,  G06F2212/1016 ,  G06F2212/60

Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.

Abstract translation: 描述的MSMC（多核共享内存控制器）是一种旨在管理多处理器内核，其他母盘外设或DMA之间的流量的模块，以及多核SoC中的EMIF（外部存储器间隔）。 本发明在仲裁事务之前统一属于从属方的所有事务大小，以便降低仲裁过程的复杂性，并在所有主机之间提供最佳的带宽管理。 每个缓存行访问分配两个连续的插槽，以自动保证单个高速缓存行内所有事务的原子性。 消除了对特定SRAM的所有存储体之间同步的需要，因为通过分配背靠背槽来实现同步。

公开(公告)号：US20140115273A1

公开(公告)日：2014-04-24

申请号：US14061508

申请日：2013-10-23

Applicant: Texas Instruments Incorporated

Inventor： Kai Chirca ,  Matthew D. Pierson

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F11/2289 ,  G06F12/0284 ,  G06F13/1668 ,  G06F13/1673 ,  G06F2212/6042

Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace)in a multicore SoC. Each processor has an associated return buffer allowing out of order responses of memory read data and cache snoop responses to ensure maximum bandwidth at the endpoints, and all endpoints receive status messages to simplify the return queue.

Abstract translation: 描述的MSMC（多核共享存储器控制器）是一种旨在管理多处理器内核，其他母盘外设或DMA之间流量的模块，以及多核SoC中的EMIF（外部存储器间隔）。 每个处理器都有一个关联的返回缓冲区，允许存储器读取数据和高速缓存侦听响应的无序响应，以确保端点处的最大带宽，并且所有端点接收状态消息以简化返回队列。

公开(公告)号：US20140115210A1

公开(公告)日：2014-04-24

申请号：US14056729

申请日：2013-10-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Daniel B. Wu ,  Matthew D. Pierson ,  Timothy D. Anderson

IPC: G06F13/16

CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the bus protocols used by each individual processor within the attached subsystem, and can perform the appropriate protocol conversion on each processor's transactions to adapt the transaction to/from the bus protocol used by the interconnect.

Abstract translation: 在高速缓存一致主机和相干系统互连之间实现异步双域网桥。 该桥具有两个半部分，每个时钟/电源下降域主和互连中一个。 异步网桥了解连接子系统内每个处理器所使用的总线协议，并且可以对每个处理器的事务执行适当的协议转换，以使交易与互连使用的总线协议相适应。

公开(公告)号：US12072824B2

公开(公告)日：2024-08-27

申请号：US17030518

申请日：2020-09-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David M. Thompson ,  Timothy D. Anderson ,  Joseph R. M. Zbiciak ,  Abhijeet A Chachad ,  Kai Chirca ,  Matthew D. Pierson

IPC: G06F13/40 ,  G06F13/364 ,  G06F13/42 ,  H04L12/801 ,  H04L12/819 ,  H04L47/10 ,  H04L47/215

CPC classification number: G06F13/404 ,  G06F13/364 ,  G06F13/42 ,  G06F13/4282 ,  H04L47/10 ,  H04L47/215 ,  H04L47/39

Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

公开(公告)号：US11803505B2

公开(公告)日：2023-10-31

申请号：US17735255

申请日：2022-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David M. Thompson ,  Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

IPC: G06F13/42 ,  G06F13/362

CPC classification number: G06F13/4252 ,  G06F13/362

Abstract: The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.

公开(公告)号：US11036648B2

公开(公告)日：2021-06-15

申请号：US16227238

申请日：2018-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F9/34 ,  G06F11/00 ,  G06F12/0875 ,  G06F12/1045 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009

Abstract: Disclosed embodiments include a data processing apparatus having a processing core, a memory, and a streaming engine. The streaming engine is configured to receive a plurality of data elements stored in the memory and to provide the plurality of data elements as a data stream to the processing core, and includes an address generator to generate addresses corresponding to locations in the memory, a buffer to store the data elements received from the locations in the memory corresponding to the generated addresses, and an output to supply the data elements received from the memory to the processing core as the data stream.

公开(公告)号：US10795844B2

公开(公告)日：2020-10-06

申请号：US16430748

申请日：2019-06-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David M. Thompson ,  Timothy D. Anderson ,  Joseph R. M. Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

IPC: G06F13/40 ,  G06F13/42 ,  H04L12/801 ,  G06F13/364 ,  H04L12/819

Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

公开(公告)号：US20170153890A1

公开(公告)日：2017-06-01

申请号：US15429205

申请日：2017-02-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet A. Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/10 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452 ,  G06F2212/60

Abstract: This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

公开(公告)号：US09489314B2

公开(公告)日：2016-11-08

申请号：US14061965

申请日：2013-10-24

Applicant: Texas Instruments Incorporated

Inventor： Kai Chirca ,  Matthew D. Pierson ,  Timothy D. Anderson

IPC: G06F13/00 ,  G06F12/10 ,  G06F12/08 ,  G06F13/16 ,  H04L29/06 ,  G06F13/42 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: This invention is an integrated memory controller/interconnect that provides very high bandwidth access to both on-chip memory and externally connected off-chip memory. This invention includes an arbitration for all memory endpoints including priority, fairness, and starvation bounds; virtualization; and error detection and correction hardware to protect the on-chip SRAM banks including automated scrubbing.

Abstract translation: 本发明是集成的存储器控​​制器/互连，其提供对片上存储器和外部连接的片外存储器的非常高的带宽访问。 本发明包括对所有存储端点的仲裁，包括优先权，公平性和饥饿限制; 虚拟化; 以及错误检测和校正硬件来保护片上SRAM库，包括自动擦洗。

公开(公告)号：US20160162407A1

公开(公告)日：2016-06-09

申请号：US15047318

申请日：2016-02-18

Applicant: Texas Instruments Incorporated

Inventor： Matthew D. Pierson ,  Kai Chirca

IPC: G06F12/08

CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The coherence controller is distributed across all coherent endpoints. The coherence controller for each memory endpoint keeps a state around for each coherent access to ensure the proper ordering of events. The coherence controller of this invention uses First-In-First-Out allocation to ensure full utilization of the resources before stalling and simplicity of implementation. The coherence controller provides Snoop Command/Response ID Allocation per memory endpoint.

Abstract translation: 本发明优化了非共享访问，避免了相干端点之间的依赖关系，即使在共享时也能确保系统的带宽。 相干控制器分布在所有相干端点上。 每个存储器端点的相干控制器保持每个相干访问的状态，以确保事件的正确排序。 本发明的一致性控制器使用先入先出分配来确保资源的充分利用在停止和简单实现之前。 相干控制器提供每个内存端点的Snoop命令/响应ID分配。