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公开(公告)号：US20230325579A1
公开(公告)日：2023-10-12
申请号：US18334551
申请日：2023-06-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Ming Chang , Shinn-Sheng Yu , Jue-Chin Yu , Ping-Chieh Wu
IPC: G06F30/398 , G03F1/36 , G03F7/20
CPC classification number: G06F30/398 , G03F7/70433 , G03F1/36
Abstract: A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.
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公开(公告)号：US11429027B2
公开(公告)日：2022-08-30
申请号：US16534965
申请日：2019-08-07
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Shinn-Sheng Yu , Ru-Gun Liu , Hsu-Ting Huang , Chin-Hsiang Lin
Abstract: An extreme ultraviolet lithography (EUVL) method includes providing at least two phase-shifting mask areas having a same pattern. A resist layer is formed over a substrate. An optimum exposure dose of the resist layer is determined, and a latent image is formed on a same area of the resist layer by a multiple exposure process. The multiple exposure process includes a plurality of exposure processes and each of the plurality of exposure processes uses a different phase-shifting mask area from the at least two phase-shifting mask areas having a same pattern.
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公开(公告)号：US11295056B2
公开(公告)日：2022-04-05
申请号：US17144975
申请日：2021-01-08
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Shinn-Sheng Yu
IPC: G06F30/398 , G03F1/36 , G03F7/20
Abstract: A method of enhancing a layout pattern includes determining a target layout pattern comprising a disk shape pattern associated with an opening. The method includes defining a polygon having a plurality of vertices on the disk shape pattern. The plurality of vertices coincide with a boundary of the disk shape pattern and the polygon is an initial layout pattern of the opening. The method includes performing an iterative correction of the initial layout pattern. The iterative correction includes projecting the layout pattern of the opening onto a substrate, determining an error between the target layout pattern and the projected layout pattern, and adjusting the layout pattern by moving the vertices of the polygon to generate a next iteration of the layout pattern. The method includes continuing the adjusting, projecting, and determining until a criterion is satisfied and a final iteration of the layout pattern of the opening is generated.
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Patent Agency Ranking
24.发明授权公开(公告)号：US10976655B2
公开(公告)日：2021-04-13
申请号：US16908449
申请日：2020-06-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-Cheng Lu , Shinn-Sheng Yu , Jeng-Horng Chen , Anthony Yen
Abstract: A lithography system includes a radiation source configured to generate an extreme ultraviolet (EUV) light. The lithography system includes a mask that defines one or more features of an integrated circuit (IC). The lithography system includes an illuminator configured to direct the EUV light onto the mask. The mask diffracts the EUV light into a 0-th order ray and a plurality of higher order rays. The lithography system includes a wafer stage configured to secure a wafer that is to be patterned according to the one or more features defined by the mask. The lithography system includes a pupil phase modulator positioned in a pupil plane that is located between the mask and the wafer stage. The pupil phase modulator is configured to change a phase of the 0-th order ray.
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25.发明授权公开(公告)号：US10691014B2
公开(公告)日：2020-06-23
申请号：US16220324
申请日：2018-12-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-Cheng Lu , Shinn-Sheng Yu , Jeng-Horng Chen , Anthony Yen
Abstract: A lithography system includes a radiation source configured to generate an extreme ultraviolet (EUV) light. The lithography system includes a mask that defines one or more features of an integrated circuit (IC). The lithography system includes an illuminator configured to direct the EUV light onto the mask. The mask diffracts the EUV light into a 0-th order ray and a plurality of higher order rays. The lithography system includes a wafer stage configured to secure a wafer that is to be patterned according to the one or more features defined by the mask. The lithography system includes a pupil phase modulator positioned in a pupil plane that is located between the mask and the wafer stage. The pupil phase modulator is configured to change a phase of the 0-th order ray.
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公开(公告)号：US09870612B2
公开(公告)日：2018-01-16
申请号：US15254607
申请日：2016-09-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shinn-Sheng Yu , Anthony Yen , Wen-Chuan Wang , Sheng-Chi Chin
CPC classification number: G06T7/0004 , G03F1/24 , G03F1/26 , G03F1/72 , G03F1/84 , G06T7/001 , G06T7/0081 , G06T7/11 , G06T2207/10004 , G06T2207/10056 , G06T2207/30148 , H01L21/0273
Abstract: A method includes inspecting a mask to locate a defect region for a defect of the mask. A phase distribution of an aerial image of the defect region is acquired. A point spread function of an imaging system is determined. One or more repair regions of the mask are identified based on the phase distribution of the aerial image of the defect region and the point spread function. A repair process is performed to the one or more repair regions of the mask to form one or more repair features.
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公开(公告)号：US20150309405A1
公开(公告)日：2015-10-29
申请号：US14259194
申请日：2014-04-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Tsung Shih , Benjamin Lee , Chia-Jen Chen , Shang-Chieh Chien , Shinn-Sheng Yu , Jeng-Horng Chen , Anthony Yen
CPC classification number: G03F1/64 , B29C71/02 , B29C2071/022 , G03F1/62 , G03F7/2002
Abstract: The present disclosure relates to a method of forming an EUV pellicle having an pellicle film connected to a pellicle frame without a supportive mesh, and an associated apparatus. In some embodiments, the method is performed by forming a cleaving plane within a substrate at a position parallel to a top surface of the substrate. A pellicle frame is attached to the top surface of the substrate. The substrate is cleaved along the cleaving plane to form a pellicle film comprising a thinned substrate coupled to the pellicle frame. Prior to cleaving the substrate, the substrate is operated upon to reduce structural damage to the top surface of substrate during formation of the cleaving plane and/or during cleaving the substrate. Reducing structural damage to the top surface of the substrate improves the durability of the thinned substrate and removes a need for a support structure for the pellicle film.
Abstract translation: 本发明涉及一种形成具有连接到没有支撑网的防护薄膜框架的防护薄膜组件的EUV防护薄膜组件的方法，以及相关联的装置。 在一些实施例中，该方法通过在平行于衬底顶表面的位置处在衬底内形成切割平面来进行。 防护薄膜组件框架附接到基板的顶表面。 基底沿着切割平面切割以形成防护薄膜，该薄膜包含连接到防护薄膜框架上的薄化基底。 在切割基板之前，操作基板以在形成切割平面期间和/或在分离基板期间减少对基板顶表面的结构损伤。 降低对基板顶表面的结构损伤提高了薄板基板的耐久性，并且消除了对防护薄膜的支撑结构的需要。
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28.发明授权Extreme ultraviolet (EUV) mask, method of fabricating the EUV mask and method of inspecting the EUV mask 有权极紫外（EUV）掩模，制造EUV掩模的方法和检查EUV掩模的方法公开(公告)号：US09081288B2
公开(公告)日：2015-07-14
申请号：US13955164
申请日：2013-07-31
Applicant: Taiwan Semiconductor Manufacturing Co., LTD.
Inventor： Chih-Tsung Shih , Yen-Cheng Lu , Shinn-Sheng Yu , Jeng-Horng Chen , Anthony Yen
Abstract: An out-of-band (OoB) suppression layer is applied on a reflective multiplayer (ML) coating, so as to avoid the OoB reflection and to enhance the optical contrast at 13.5 nm. A material having a low reflectivity at wavelength of 193-257 nm, for example, silicon carbide (SiC), is used as the OoB suppression layer. A method of fabricating an EUV mask having the OoB suppression layer and a method of inspecting an EUV mask having the OoB suppression are also provided.
Abstract translation: 将带外（OoB）抑制层施加在反射多人（ML）涂层上，以避免OoB反射并增强13.5nm处的光学对比度。 使用波长为193-257nm的低反射率的材料，例如碳化硅（SiC），作为OoB抑制层。 还提供了制造具有OoB抑制层的EUV掩模的方法和检查具有OoB抑制的EUV掩模的方法。
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