公开(公告)号：US11488857B2

公开(公告)日：2022-11-01

申请号：US16906615

申请日：2020-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US11450741B2

公开(公告)日：2022-09-20

申请号：US17201041

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/417

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US11450565B2

公开(公告)日：2022-09-20

申请号：US16997616

申请日：2020-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Cheng Chen ,  Huicheng Chang ,  Fu-Ming Huang ,  Kei-Wei Chen ,  Liang-Yin Chen ,  Tang-Kuei Chang ,  Yee-Chia Yeo ,  Wei-Wei Liang ,  Ji Cui

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L23/535 ,  H01L23/532

Abstract: The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

公开(公告)号：US11257906B2

公开(公告)日：2022-02-22

申请号：US16889356

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Liang-Yin Chen

IPC: H01L29/08 ,  H01L29/36 ,  H01L29/417 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02 ,  H01L21/223 ,  H01L21/324 ,  H01L29/45 ,  H01L29/66

Abstract: Embodiments disclosed herein relate generally to forming a source/drain region with a high surface dopant concentration at an upper surface of the source/drain region, to which a conductive feature may be formed. In an embodiment, a structure includes an active area on a substrate, a dielectric layer over the active area, and a conductive feature through the dielectric layer to the active area. The active area includes a source/drain region. The source/drain region includes a surface dopant region at an upper surface of the source/drain region, and includes a remainder portion of the source/drain region having a source/drain dopant concentration. The surface dopant region includes a peak dopant concentration proximate the upper surface of the source/drain region. The peak dopant concentration is at least an order of magnitude greater than the source/drain dopant concentration. The conductive feature contacts the source/drain region at the upper surface of the source/drain region.

公开(公告)号：US12087578B2

公开(公告)日：2024-09-10

申请号：US17651851

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hung Wu ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/0273 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of forming a semiconductor device includes forming a photoresist over a target layer, where the target layer includes a substrate. The photoresist is patterned to form a patterned photoresist. Scum remains between portions of the patterned photoresist. The substrate is tilted relative to a direction of propagation of an ion beam. An ion treatment is performed on the scum. A pattern of the patterned photoresist is transferred to the target layer.

公开(公告)号：US12051619B2

公开(公告)日：2024-07-30

申请号：US17871042

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76825 ,  H01L21/76804 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/5329

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US12015055B2

公开(公告)日：2024-06-18

申请号：US18350838

申请日：2023-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L29/167 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US20230352533A1

公开(公告)日：2023-11-02

申请号：US18350838

申请日：2023-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/167 ,  H01L21/285

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US11796922B2

公开(公告)日：2023-10-24

申请号：US16587710

申请日：2019-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Jyu-Horng Shieh ,  Liang-Yin Chen ,  Shu-Huei Suen ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yi-Nien Su ,  Yung-Sung Yen ,  Chia-Fong Chang ,  Ya-Wen Yeh ,  Yu-Tien Shen

IPC: G03F1/22 ,  G03F7/36 ,  G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  G03F1/36 ,  G03F1/70

CPC classification number: G03F7/70558 ,  G03F1/22 ,  G03F1/36 ,  G03F1/70 ,  G03F7/0035 ,  G03F7/40 ,  G03F7/70033 ,  G03F7/70625 ,  H01L21/0274

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

公开(公告)号：US11610885B2

公开(公告)日：2023-03-21

申请号：US16924541

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chia-Ling Chan ,  Liang-Yin Chen ,  Huicheng Chang

IPC: H01L21/265 ,  H01L21/22 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84

Abstract: A method for forming a semiconductor structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes depositing a dopant source layer over the gate structure. The method also includes driving dopants of the dopant source layer into the fin structure. The method also includes removing the dopant source layer. The method also includes annealing the dopants in the fin structure to form a doped region. The method also includes etching the doped region and the fin structure below the doped region to form a recess. The method also includes growing a source/drain feature in the recess.