公开(公告)号：US20200273773A1

公开(公告)日：2020-08-27

申请号：US16283852

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chao-Wen Shih ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Sen-Kuei Hsu

IPC: H01L23/373 ,  H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q1/02

Abstract: A semiconductor device including a chip package and an antenna package disposed on the chip package is provided. The chip package includes a semiconductor chip, an encapsulation enclosing the semiconductor chip, and a redistribution structure disposed on the semiconductor chip and the encapsulation and electrically coupled to the semiconductor chip. The antenna package includes an antenna pattern electrically coupled to the chip package, and an intermediate structure disposed between the antenna pattern and the chip package, wherein the intermediate structure comprises a ceramic element in contact with the redistribution structure and thermally dissipating a heat generated from the semiconductor chip.

公开(公告)号：US10720416B2

公开(公告)日：2020-07-21

申请号：US16103938

申请日：2018-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Chen ,  Chih-Hua Chen ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Lipu Kris Chuang ,  Tin-Hao Kuo

IPC: H01L21/56 ,  H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/34 ,  H01L23/31 ,  H01L25/18

Abstract: A semiconductor device includes a bottom package, a top package, and a heat dissipating structure. The bottom package includes a redistribution structure, and a die disposed on a first surface of the redistribution structure and electrically connected to the redistribution structure. The top package is disposed on a second surface of the redistribution structure opposite to the first surface. The heat dissipating structure is disposed over the bottom package, and includes a thermal relaxation block. The thermal relaxation block contacts the redistribution structure and is disposed beside the top package.

公开(公告)号：US20200091097A1

公开(公告)日：2020-03-19

申请号：US16133705

申请日：2018-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tuan-Yu Hung ,  Hung-Jui Kuo ,  Hsin-Yu Pan ,  Ming-che Ho ,  Tzu Yun Huang ,  Yen-Fu Su

IPC: H01L23/00

Abstract: A package structure is provided. The package structure includes a dielectric layer on a die, a RDL structure and a conductive terminal. The RDL structure comprises a redistribution layer in and on the dielectric layer. The redistribution layer comprises a via and a conductive plate. The via is located in and penetrating through the dielectric layer to be connected to the die. The conductive plate is on the via and the dielectric layer, and is connected to the die through the via. The conductive terminal is electrically connected to the die through the RDL structure. The via is ring-shaped.

公开(公告)号：US20200058632A1

公开(公告)日：2020-02-20

申请号：US16103938

申请日：2018-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Chen ,  Chih-Hua Chen ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Lipu Kris Chuang ,  Tin-Hao Kuo

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/34 ,  H01L21/56

Abstract: A semiconductor device includes a bottom package, a top package, and a heat dissipating structure. The bottom package includes a redistribution structure, and a die disposed on a first surface of the redistribution structure and electrically connected to the redistribution structure. The top package is disposed on a second surface of the redistribution structure opposite to the first surface. The heat dissipating structure is disposed over the bottom package, and includes a thermal relaxation block. The thermal relaxation block contacts the redistribution structure and is disposed beside the top package.

公开(公告)号：US11894299B2

公开(公告)日：2024-02-06

申请号：US17188787

申请日：2021-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Wen Shih ,  Chen-Hua Yu ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Sen-Kuei Hsu

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/525 ,  H01L21/56 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/5225 ,  H01L23/5329 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76885 ,  H01L23/5286 ,  H01L24/13 ,  H01L2224/0348 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/11622 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16104 ,  H01L2224/03462 ,  H01L2924/00014

Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

公开(公告)号：US20230223357A1

公开(公告)日：2023-07-13

申请号：US17752272

申请日：2022-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Che Chiang ,  Chien-Hsun Chen ,  Tuan-Yu Hung ,  Hsin-Yu Pan ,  Wei-Kang Hsieh ,  Tsung-Hsien Chiang ,  Chao-Hsien Huang ,  Tzu-Sung Huang ,  Ming Hung Tseng ,  Wei-Chih Chen ,  Ban-Li Wu ,  Hao-Yi Tsai ,  Yu-Hsiang Hu ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L25/105 ,  H01L24/20 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L24/19 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2224/214 ,  H01L2221/68359 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.

公开(公告)号：US11450581B2

公开(公告)日：2022-09-20

申请号：US17162073

申请日：2021-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Teng-Yuan Lo ,  Lipu Kris Chuang ,  Hsin-Yu Pan

IPC: H01L23/24 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

公开(公告)号：US20220020655A1

公开(公告)日：2022-01-20

申请号：US16933910

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Wei Cheng ,  Jiun-Yi Wu ,  Hsin-Yu Pan ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Wei-Yu Chen

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/40

Abstract: A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.

公开(公告)号：US11004812B2

公开(公告)日：2021-05-11

申请号：US16133705

申请日：2018-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tuan-Yu Hung ,  Hung-Jui Kuo ,  Hsin-Yu Pan ,  Ming-che Ho ,  Tzu Yun Huang ,  Yen-Fu Su

IPC: H01L23/00

Abstract: A package structure is provided. The package structure includes a dielectric layer on a die, a RDL structure and a conductive terminal. The RDL structure comprises a redistribution layer in and on the dielectric layer. The redistribution layer comprises a via and a conductive plate. The via is located in and penetrating through the dielectric layer to be connected to the die. The conductive plate is on the via and the dielectric layer, and is connected to the die through the via. The conductive terminal is electrically connected to the die through the RDL structure. The via is ring-shaped.

公开(公告)号：US20210118847A1

公开(公告)日：2021-04-22

申请号：US16655237

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lipu Kris Chuang ,  Chung-Hao Tsai ,  Hsin-Yu Pan ,  Yi-Che Chiang ,  Chien-Chang Lin

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/367 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: A memory module includes a first redistribution structure, a second redistribution structure, first semiconductor dies, second semiconductor dies, an encapsulant, through insulator vias and thermally conductive material. Second redistribution structure is stacked over first redistribution structure. First semiconductor dies are sandwiched between first redistribution structure and second redistribution structure and disposed side by side. Second semiconductor dies are disposed on the second redistribution structure. The encapsulant laterally wraps the second semiconductor dies. The through insulator vias are disposed among the first semiconductor dies, extending from the first redistribution structure to the second redistribution structure. The through insulator vias are electrically connected to the first redistribution structure and the second redistribution structure. The thermally conductive material is disposed on the second redistribution structure, among the second semiconductor dies and overlying the through insulator vias. The thermally conductive material has a thermal conductivity larger than that of the encapsulant.