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    Semiconductor structure and manufacturing method thereof
    21.
    发明授权
    Semiconductor structure and manufacturing method thereof 有权

    公开(公告)号：US11094613B2

    公开(公告)日：2021-08-17

    申请号：US16547606

    申请日：2019-08-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chia Hu ,  Hsien-Wei Chen ,  Ming-Fa Chen ,  Sen-Bor Jan

    IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

    Abstract: A semiconductor structure and the manufacturing method thereof are provided. A semiconductor structure includes a semiconductor substrate, a plurality of interconnecting layers, a first connector, and a second connector. The semiconductor substrate includes a plurality of semiconductor devices therein. The interconnecting layers are disposed over the semiconductor substrate and electrically coupled to the semiconductor devices. The first connector is disposed over the plurality of interconnecting layers and extends to be in contact with a first level of the plurality of interconnecting layers. The second connector is disposed over the plurality of interconnecting layers and substantially leveled with the first connector. The second connector extends further than the first connector to be in contact with a second level of the plurality of interconnecting layers between the first level of the plurality of interconnecting layers and the semiconductor substrate, and the first connector is wider than the second connector.

    Semiconductor Device and Method of Manufacture
    22.
    发明申请
    Semiconductor Device and Method of Manufacture 有权

    公开(公告)号：US20210175154A1

    公开(公告)日：2021-06-10

    申请号：US17181784

    申请日：2021-02-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chia Hu ,  Sen-Bor Jan ,  Hsien-Wei Chen ,  Ming-Fa Chen

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L21/768 ,  H01L21/66

    Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.

    Layout design of integrated circuit with through-substrate via
    27.
    发明授权
    Layout design of integrated circuit with through-substrate via 有权

    公开(公告)号：US11080455B1

    公开(公告)日：2021-08-03

    申请号：US16924195

    申请日：2020-07-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chia Hu ,  Ming-Fa Chen ,  Sen-Bor Jan ,  Meng-Wei Chiang

    IPC: G06F30/392 ,  H01L23/48 ,  G06F119/06 ,  H01L27/088 ,  H01L29/06

    Abstract: A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.

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