公开(公告)号：US09171759B2

公开(公告)日：2015-10-27

申请号：US13717883

申请日：2012-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Pin Cheng ,  Jung-Liang Chien ,  Chih-Kang Chao ,  Chi-Cherng Jeng ,  Hsin-Chi Chen ,  Ying-Lang Wang

IPC: H01L21/78 ,  H01L23/00 ,  H01L23/58 ,  H01L21/66

CPC classification number: H01L21/78 ,  H01L22/32 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/00

Abstract: A semiconductor wafer having a plurality of chip die areas arranged on a wafer in an array, each chip die area including a seal ring area with one or more first sets of polygonal structures. The wafer further comprises scribe line areas between the chip die areas, the scribe line areas including one or more second sets of polygonal structures. The presence of proximate polygonal structures between the scribe line and seal ring areas balance stresses between the chip die areas during wafer dicing operation.

Abstract translation: 一种半导体晶片，具有排列在阵列中的晶片上的多个芯片晶粒区域，每个芯片晶粒区域包括具有一个或多个第一组多边形结构的密封环区域。 晶片还包括在芯片模具区域之间的划线区域，划线区域包括一个或多个第二组多边形结构。 切割线和密封环区域之间的近似多边形结构的存在在晶片切割操作期间平衡芯片晶片区域之间的应力。

公开(公告)号：US20140167197A1

公开(公告)日：2014-06-19

申请号：US13718688

申请日：2012-12-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shiu-Ko JangJian ,  Chi-Cherng Jeng ,  Volume Chien ,  Ying-Lang Wang

IPC: H01L31/0216 ,  H01L31/18

CPC classification number: H01L27/14687 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14685 ,  H01L31/18

Abstract: A backside illumination image sensor structure comprises an image sensor formed adjacent to a first side of a semiconductor substrate, wherein an interconnect layer is formed over the first side of the semiconductor substrate, a backside illumination film formed over a second side of the semiconductor substrate, a metal shielding layer formed over the backside illumination film and a via embedded in the backside illumination film and coupled between the metal shielding layer and the semiconductor substrate.

Abstract translation: 背面照明图像传感器结构包括与半导体衬底的第一侧相邻形成的图像传感器，其中在所述半导体衬底的第一侧上形成有互连层，形成在所述半导体衬底的第二侧上的背面照明膜， 形成在背面照明膜上的金属屏蔽层和嵌入在背面照明膜中并且连接在金属屏蔽层和半导体基板之间的通孔。

公开(公告)号：US20240088225A1

公开(公告)日：2024-03-14

申请号：US18508788

申请日：2023-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Wen-Yen Chen ,  Li-Heng Chen ,  Li-Ting Wang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Ying-Lang Wang

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/161 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

公开(公告)号：US20230197852A1

公开(公告)日：2023-06-22

申请号：US18174045

申请日：2023-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Wen-Yen Chen ,  Ying-Lang Wang ,  Liang-Yin Chen ,  Li-Ting Wang ,  Huicheng Chang

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L21/76829 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/6681 ,  H01L21/02694 ,  H01L21/823864

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

公开(公告)号：US11621342B2

公开(公告)日：2023-04-04

申请号：US17068578

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih Hung Chen ,  Kei-Wei Chen ,  Ying-Lang Wang

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/67 ,  H01L21/321 ,  B24B37/00 ,  B24B37/10 ,  B24B7/22 ,  H01L29/08

Abstract: In an embodiment, a method includes: performing a self-limiting process to modify a top surface of a wafer; after the self-limiting process completes, removing the modified top surface from the wafer; and repeating the performing the self-limiting process and the removing the modified top surface from the wafer until a thickness of the wafer is decreased to a predetermined thickness.

公开(公告)号：US10916481B2

公开(公告)日：2021-02-09

申请号：US16017665

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih Hung Chen ,  Kei-Wei Chen ,  Ying-Lang Wang

IPC: H01L21/66 ,  H01L21/321 ,  B24B37/013 ,  G01B7/06

Abstract: Various embodiments provide a thickness sensor and method for measuring a thickness of discrete conductive features, such as conductive lines and plugs. In one embodiment, the thickness sensor generates an Eddy current in a plurality of discrete conductive features, and measures the generated Eddy current generated in the discrete conductive features. The thickness sensor has a small sensor spot size, and amplifies peaks and valleys of the measured Eddy current. The thickness sensor determines a thickness of the discrete conductive features based on a difference between a minimum amplitude value and a maximum amplitude value of the measured Eddy current.

公开(公告)号：US20200091425A1

公开(公告)日：2020-03-19

申请号：US16693946

申请日：2019-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ting Chu ,  Tong-Chern Ong ,  Ying-Lang Wang

IPC: H01L45/00

Abstract: The present disclosure, in some embodiments, relates to a method of forming a resistive random access memory (RRAM) device. The method includes forming one or more bottom electrode films over a lower interconnect layer within a lower inter-level dielectric layer. A data storage film having a variable resistance is formed above the one or more bottom electrode films. A lower top electrode film including a metal is over the data storage film, one or more oxygen barrier films are over the lower top electrode film, and an upper top electrode film including a metal nitride is formed over the one or more oxygen barrier films The one or more oxygen barrier films include one or more of a metal oxide film and a metal oxynitride film. The upper top electrode film is formed to be completely confined over a top surface of the one or more oxygen barrier films.

公开(公告)号：US20200058858A1

公开(公告)日：2020-02-20

申请号：US16662422

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ting Chu ,  Tong-Chern Ong ,  Ying-Lang Wang

IPC: H01L45/00

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a bottom electrode that is disposed over a lower interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A data storage structure is arranged over the bottom electrode and a multi-layer top electrode is disposed over the data storage structure. The multi-layer top electrode includes conductive top electrode layers separated by an oxygen barrier structure that is configured to mitigate movement of oxygen between the conductive top electrode layers. A sidewall spacer is disposed directly over the bottom electrode and has a sidewall that covers outermost sidewalls of the conductive top electrode layers and the oxygen barrier structure.

公开(公告)号：US09871100B2

公开(公告)日：2018-01-16

申请号：US14812864

申请日：2015-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Ming Lin ,  Shiu-Ko Jangjian ,  Chun-Che Lin ,  Ying-Lang Wang ,  Wei-Ken Lin ,  Chuan-Pu Liu

IPC: H01L29/06 ,  H01L27/08 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/324 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/785

Abstract: A trench structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The substrate has a trench therein. The isolation structure is disposed in the trench. The liner layer is disposed between the substrate and the isolation structure. The liner layer includes nitrogen, and the liner layer has spatially various nitrogen concentration.

公开(公告)号：US20150200299A1

公开(公告)日：2015-07-16

申请号：US14224961

申请日：2014-03-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Chih CHEN ,  Ying-Lang Wang ,  Chih-Mu Huang ,  Ying-Hao Chen ,  Wen-Chang Kuo ,  Jung-Chi Jeng

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.

Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件包括衬底; 在衬底中具有第一掺杂剂的源/漏区; 阻挡层，其具有形成在衬底中的源极/漏极区周围的第二掺杂物。 当半导体器件按比例缩小时，源极/漏极区域中的掺杂分布可能影响阈值电压均匀性，所提供的半导体器件可以通过阻挡层来改善阈值电压均匀性以控制掺杂分布。