公开(公告)号：US20230282247A1

公开(公告)日：2023-09-07

申请号：US18316743

申请日：2023-05-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chieh Lee ,  Yi-Ching Liu ,  Chia-En Huang ,  Jen-Yuan Chang ,  Yih Wang

IPC分类号： G11C5/06 ,  G11C5/02 ,  H01L23/48 ,  H10B12/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00

CPC分类号： G11C5/06 ,  G11C5/025 ,  H01L23/481 ,  H10B12/00 ,  H10B61/00 ,  H10B63/84 ,  H10N50/01 ,  H10N50/80 ,  H10N70/011 ,  H10N70/821

摘要： A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.

公开(公告)号：US11749664B2

公开(公告)日：2023-09-05

申请号：US17811903

申请日：2022-07-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Yi-Ching Liu ,  Yih Wang ,  Chia-En Huang

IPC分类号： H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  G11C7/10 ,  G11C8/10 ,  G11C8/08

CPC分类号： H01L25/18 ,  G11C7/1069 ,  G11C7/1096 ,  G11C8/08 ,  G11C8/10 ,  H01L23/3157 ,  H01L24/24 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2924/1431 ,  H01L2924/1434

摘要： A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.

公开(公告)号：US11676641B2

公开(公告)日：2023-06-13

申请号：US17461332

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chieh Lee ,  Yi-Ching Liu ,  Chia-En Huang ,  Chang Jen-Yuan ,  Yih Wang

IPC分类号： G11C5/06 ,  G11C5/02 ,  H01L23/48 ,  H01L27/24 ,  H01L43/12 ,  H01L45/00 ,  H01L27/108 ,  H01L27/22 ,  H01L43/02

CPC分类号： G11C5/06 ,  G11C5/025 ,  H01L23/481 ,  H01L27/108 ,  H01L27/222 ,  H01L27/2481 ,  H01L43/02 ,  H01L43/12 ,  H01L45/122 ,  H01L45/16

摘要： A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.

公开(公告)号：US20230061700A1

公开(公告)日：2023-03-02

申请号：US17461278

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Ching Liu ,  Yih Wang

IPC分类号： G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  G11C16/24

摘要： Disclosed herein are related to a memory array including one-time programmable (OTP) cells. In one aspect, the memory array includes a set of OTP cells including a first subset of OTP cells connected between a first program control line and a first read control line. Each OTP cell of the first subset of OTP cells may include a programmable storage device and a switch connected between the first program control line and the first read control line. The first program control line may extend towards a first side of the memory array along a first direction, and the first read control line may extend towards a second side of the memory array facing away from the first side of the memory array.

公开(公告)号：US20230038021A1

公开(公告)日：2023-02-09

申请号：US17582001

申请日：2022-01-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Han Lin ,  Chia-En Huang ,  Han-Jong Chia ,  Yi-Ching Liu ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L23/522

摘要： A memory device includes a first signal line, a second signal line, a first memory cell and a plurality of second memory cells. The first memory cell is coupled to the first signal line. Each of the second memory cells has a first terminal coupled to the first signal line through the first memory cell and a second terminal coupled to the second signal line.

公开(公告)号：US20230022115A1

公开(公告)日：2023-01-26

申请号：US17726086

申请日：2022-04-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chieh Lee ,  Chia-En Huang ,  Yi-Ching Liu ,  Wen-Chang Cheng ,  Yih Wang

IPC分类号： H01L27/11597 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11592 ,  G11C5/04 ,  G11C5/06

摘要： In some embodiments, an integrated circuit (IC) device includes an active semiconductor layer, a circuitry formed within the active semiconductor layer, a region including conductive layers formed above the active semiconductor layer, and a memory module formed in the region. The memory device includes a three-dimensional array of memory cells, each adapted to store a weight value, and adapted to generate at each memory cell a signal indicative of a product between the stored weight value and an input signal applied to the memory cell. The memory module is further adapted to transmit the product signals from the memory cell simultaneously in the direction of the active semiconductor layer.

公开(公告)号：US20220293158A1

公开(公告)日：2022-09-15

申请号：US17470854

申请日：2021-09-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Peng-Chun Liou ,  Zhiqiang Wu ,  Chung-Wei Wu ,  Yi-Ching Liu ,  Yih Wang

IPC分类号： G11C11/22 ,  H01L27/11597

摘要： A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures.

公开(公告)号：US11424233B1

公开(公告)日：2022-08-23

申请号：US17225913

申请日：2021-04-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Yi-Ching Liu ,  Yih Wang ,  Chia-En Huang

IPC分类号： H01L25/18 ,  H01L23/31 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  H01L23/00

摘要： A method is provided. The method includes providing a first die and a second die. The first die may include a memory array that includes a plurality of memory cells and a sensing element. The second die may include an address decoder associated with the memory array of the first die. The method also includes coupling the second die to the sensing element of the first die, and providing an encapsulant at least partially encapsulating the first die and the second die.

公开(公告)号：US20220165312A1

公开(公告)日：2022-05-26

申请号：US17572370

申请日：2022-01-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Ta Yu ,  Chia-En Huang ,  Sai-Hooi Yeong ,  Yih Wang ,  Yi-Ching Liu

IPC分类号： G11C7/02 ,  G11C7/18 ,  G11C8/08 ,  G11C7/12 ,  G11C8/14

摘要： One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.

公开(公告)号：US12068023B2

公开(公告)日：2024-08-20

申请号：US17643191

申请日：2021-12-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chieh Lee ,  Yi-Ching Liu ,  Chia-En Huang ,  Wen-Chang Cheng ,  Jonathan Tsung-Yung Chang

IPC分类号： G11C8/00 ,  G11C11/4091 ,  H10B12/00

CPC分类号： G11C11/4091 ,  H10B12/09 ,  H10B12/50

摘要： A memory structure includes a first memory array having bit lines; a second memory array having bit lines; a first sense amplifier connected to a first bit line of the first memory array and a first bit line of the second memory array; and a second sense amplifier connected to a second bit line of the first memory array and a second bit line of the second memory array. The second bit line of the first memory array is adjacent to the first bit line of the first memory array, and the second bit line of the second memory array is adjacent to the first bit line of the second memory array.