公开(公告)号：US07132355B2

公开(公告)日：2006-11-07

申请号：US10932129

申请日：2004-09-01

申请人： Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Cem Basceri ,  Eric R. Blomiley

发明人： Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Cem Basceri ,  Eric R. Blomiley

IPC分类号： H01L21/44

CPC分类号： H01L29/66787 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66742 ,  H01L29/78642

摘要： This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.

公开(公告)号：US20060231016A1

公开(公告)日：2006-10-19

申请号：US11471106

申请日：2006-06-19

申请人： Eric Blomiley ,  Nirmal Ramaswamy ,  Ross Dando ,  Joel Drewes ,  Alan Colwell ,  Eduardo Tovar

发明人： Eric Blomiley ,  Nirmal Ramaswamy ,  Ross Dando ,  Joel Drewes ,  Alan Colwell ,  Eduardo Tovar

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： H01L21/67248 ,  C23C16/481 ,  C23C16/52 ,  C30B25/165 ,  C30B31/18

摘要： The invention includes deposition apparatuses configured to monitor the temperature of a semiconductor wafer substrate by utilizing conduits which channel radiation from the substrate to a detector/signal processor system. In particular aspects, the temperature of the substrate can be measured while the substrate is spinning within a reaction chamber. The invention also includes deposition apparatuses in which flow of mixed gases is controlled by mass flow controllers provided downstream of the location where the gases are mixed and/or where flow of gases is measured with mass flow measurement devices provided downstream of the location where the gases are mixed. Additionally, the invention encompasses deposition apparatuses in which mass flow controllers and/or mass flow measurement devices are provided upstream of a header which splits a source gas into multiple paths directed toward multiple different reaction chambers.

摘要翻译： 本发明包括沉积设备，其被配置为通过利用将辐射从衬底传送到检测器/信号处理器系统的管道来监测半导体晶片衬底的温度。 在特定方面，可以在衬底在反应室内旋转的同时测量衬底的温度。 本发明还包括沉积装置，其中混合气体的流动由设置在气体混合位置下游的质量流量控制器控制，和/或在气体流量测量时，质量流量测量装置设置在气体的位置的下游 混合 此外，本发明还包括沉积装置，其中质量流量控制器和/或质量流量测量装置设置在将源气体分成多个指向多个不同反应室的路径的集管的上游。

公开(公告)号：US20060175664A1

公开(公告)日：2006-08-10

申请号：US11053475

申请日：2005-02-07

申请人： Nirmal Ramaswamy ,  Paul Castrovillo ,  Joel Drewes

发明人： Nirmal Ramaswamy ,  Paul Castrovillo ,  Joel Drewes

IPC分类号： H01L29/40 ,  H01L21/44

CPC分类号： H01L21/76855 ,  H01L21/28568 ,  H01L21/76846 ,  H01L21/76867

摘要： The invention includes methods of forming metal silicide. A layer consisting essentially of one or more metal nitrides is formed directly against a silicon-containing region. A layer comprising one or more metals is formed over the one or more metal nitrides. Silicon is transferred from the silicon-containing region, through the one or more metal nitrides, and to the one or more metals to convert at least some of the one or more metals into metal silicides. In particular aspects, titanium is formed over tantalum nitride, and the silicon is transferred into the titanium to convert the titanium into titanium silicide. The invention also includes semiconductor constructions having a layer consisting essentially of titanium silicide directly against a layer consisting essentially of tantalum nitride.

摘要翻译： 本发明包括形成金属硅化物的方法。 基本上由一种或多种金属氮化物组成的层直接形成在含硅区域上。 在一种或多种金属氮化物上形成包含一种或多种金属的层。 硅通过一种或多种金属氮化物从含硅区域转移到一种或多种金属，以将至少一种一种或多种金属转化为金属硅化物。 在特定方面，在氮化钽上形成钛，并且将硅转移到钛中以将钛转化为硅化钛。 本发明还包括半导体结构，其具有基本上由硅化钛组成的层，直接与主要由氮化钽组成的层组成。

公开(公告)号：US20060046442A1

公开(公告)日：2006-03-02

申请号：US10931924

申请日：2004-09-01

申请人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Cem Basceri ,  Eric Blomiley

发明人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Cem Basceri ,  Eric Blomiley

IPC分类号： H01L21/20

CPC分类号： H01L29/66787 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78642

摘要： The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括形成外延含硅材料的方法和形成垂直晶体管的方法。 在一个实施方案中，形成外延含硅材料的方法包括提供包括单晶材料的衬底。 单晶材料的第一部分向外暴露，而单晶材料的第二部分被掩蔽。 第一含硅层从第一部分的暴露的单晶材料而不是被掩蔽的第二部分的单晶材料外延生长。 在生长第一含硅层之后，单晶材料的第二部分被未掩蔽。 然后从第一含硅层和第二部分的未掩模的单晶材料外延生长第二含硅层。 考虑了其他方面和实现。

公开(公告)号：US06987055B2

公开(公告)日：2006-01-17

申请号：US10755000

申请日：2004-01-09

申请人： Eric R. Blomiley ,  Gurtej S. Sandhu ,  Cem Basceri ,  Nirmal Ramaswamy

发明人： Eric R. Blomiley ,  Gurtej S. Sandhu ,  Cem Basceri ,  Nirmal Ramaswamy

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639

摘要： The invention includes a method for selective deposition of semiconductor material. A substrate is placed within a reaction chamber. The substrate comprises a first surface and a second surface. The first and second surfaces are exposed to a semiconductor material precursor under conditions in which growth of semiconductor material from the precursor comprises a lag phase prior to a growth phase, and under which it takes longer for the growth phase to initiate on the second surface than on the first surface. The exposure of the first and second surfaces is conducted for a time sufficient for the growth phase to occur on the first surface, but not long enough for the growth phase to occur on the second surface.

摘要翻译： 本发明包括半导体材料的选择性沉积方法。 将基板放置在反应室内。 基板包括第一表面和第二表面。 第一表面和第二表面在半导体材料前体暴露于其中来自前体的半导体材料的生长在生长阶段之前包含滞后期的条件下，并且在该阶段生长阶段在第二表面上开始需要更长时间比 在第一个表面。 进行第一表面和第二表面的曝光足够长的时间，以使生长阶段在第一表面上发生，但是不足以使生长相发生在第二表面上。

公开(公告)号：US08846516B2

公开(公告)日：2014-09-30

申请号：US11774298

申请日：2007-07-06

申请人： Nirmal Ramaswamy

发明人： Nirmal Ramaswamy

IPC分类号： H01L21/4763 ,  H01L29/423 ,  B82Y10/00 ,  H01L21/28

CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L21/28273

摘要： Dielectric materials having implanted metal sites and methods of their fabrication have been described. Such materials are suitable for use as charge-trapping nodes of non-volatile memory cells for memory devices. By incorporating metal sites into dielectric charge-trapping materials using an ammonia plasma and a metal source in contact with the plasma, improved programming and erase voltages may be facilitated.

摘要翻译： 已经描述了具有植入金属部位的电介质材料及其制造方法。 这种材料适合用作用于存储器件的非易失性存储单元的电荷捕获节点。 通过使用氨等离子体和与等离子体接触的金属源将金属部位结合到介电电荷捕获材料中，可以促进改进的编程和擦除电压。

公开(公告)号：US08357970B2

公开(公告)日：2013-01-22

申请号：US12757727

申请日：2010-04-09

申请人： Gurtej S. Sandhu ,  Nirmal Ramaswamy

发明人： Gurtej S. Sandhu ,  Nirmal Ramaswamy

IPC分类号： H01L29/423 ,  H01L29/788 ,  H01L29/78 ,  H01L29/792

CPC分类号： H01L27/088 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833

摘要： Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around the pillar of epitaxial silicon at different levels. A control gate is formed around each of the charge storage nodes. Additional embodiments are also described.

摘要翻译： 描述了制造电荷存储晶体管的方法以及包括它们的装置和系统。 在一种这样的方法中，形成外延硅的支柱。 至少第一和第二电荷存储节点（例如，浮动栅极）以不同的水平形成在外延硅的柱周围。 在每个电荷存储节点周围形成控制栅极。 还描述了另外的实施例。

公开(公告)号：US20120319172A1

公开(公告)日：2012-12-20

申请号：US13598258

申请日：2012-08-29

申请人： Nirmal Ramaswamy ,  Gurtej S. Sandhu

发明人： Nirmal Ramaswamy ,  Gurtej S. Sandhu

IPC分类号： H01L29/788 ,  H01L27/088 ,  H01L21/28

CPC分类号： H01L21/28282 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Inside the vertical opening a substantially vertical structure may be formed that comprises a first layer, a charge-trap layer, a tunneling oxide layer, and an epitaxial silicon portion. Additional embodiments are also described.

摘要翻译： 描述了制造3D电荷陷阱存储器单元的方法，以及包括它们的装置和系统。 在由导电和绝缘材料的交替层形成的平面堆叠中，可以形成基本垂直的开口。 在垂直开口内部，可以形成包括第一层，电荷陷阱层，隧道氧化物层和外延硅部分的基本垂直的结构。 还描述了另外的实施例。

公开(公告)号：US20120007037A1

公开(公告)日：2012-01-12

申请号：US12833314

申请日：2010-07-09

申请人： Nirmal Ramaswamy ,  Kirk D. Prall

发明人： Nirmal Ramaswamy ,  Kirk D. Prall

IPC分类号： H01L45/00

CPC分类号： H01L45/14 ,  G11C13/0004 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/145

摘要： Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further include an interface on the silicon material of ruthenium or ruthenium silicide. A ruthenium silicide interface may be a polycrystalline ruthenium silicide.

摘要翻译： 利用存储单元的存储器件，其中包括电阻元件和耦合在两个导体之间的二极管。 二极管包括钌材料和硅材料。 二极管还包括硅材料上的钌或钌化硅的界面。 硅化钌界面可以是多晶硅化钌。

公开(公告)号：US20110133265A1

公开(公告)日：2011-06-09

申请号：US13025338

申请日：2011-02-11

申请人： Garo Derderian ,  Nirmal Ramaswamy

发明人： Garo Derderian ,  Nirmal Ramaswamy

IPC分类号： H01L29/788 ,  H01L29/772

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336

摘要： A memory cell has a tunnel dielectric over a first silicon-containing material, a second silicon-containing material over the tunnel dielectric, a first silicon oxide layer on an edge of the second silicon-containing material and extending across a first portion of an edge of the tunnel dielectric, and a second silicon oxide layer on a side of the first silicon-containing material and extending across a second portion of the edge of the tunnel dielectric. The first and second silicon oxide layers are two distinct layers and are in contact with the tunnel dielectric layer.

摘要翻译： 存储器单元在第一含硅材料上方具有隧道电介质，在隧道电介质上方的第二含硅材料，在第二含硅材料的边缘上的第一氧化硅层，并且跨越第一含硅材料的第一部分 并且在第一含硅材料的一侧上延伸并延伸穿过隧道电介质边缘的第二部分的第二氧化硅层。 第一和第二氧化硅层是两个不同的层，并且与隧道介电层接触。