公开(公告)号：US20080081380A1

公开(公告)日：2008-04-03

申请号：US11706722

申请日：2007-02-15

Applicant: Francis Gabriel Celii ,  Kezhakkedath R. Udayakumar ,  Gregory B. Shinn ,  Theodore S. Moise ,  Scott R. Summerfelt

Inventor： Francis Gabriel Celii ,  Kezhakkedath R. Udayakumar ,  Gregory B. Shinn ,  Theodore S. Moise ,  Scott R. Summerfelt

IPC: H01L21/00

CPC classification number: H01L28/75 ,  H01L27/11507 ,  H01L28/55

Abstract: A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.

Abstract translation: 提供一种用于制造铁电电容器结构的方法，其包括在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法。 该方法包括蚀刻上电极的部分，蚀刻铁电材料，并蚀刻下电极以限定图案化的铁电电容器结构，以及蚀刻下电极扩散阻挡结构的一部分。 所述方法还包括使用第一灰化过程灰化所述图案化的铁电电容器结构，其中所述灰分包括含氧/氮/水的灰分，在所述第一灰化处理之后执行湿式清洁处理，以及使用 第二次灰化过程。

公开(公告)号：US06902939B2

公开(公告)日：2005-06-07

申请号：US10223643

申请日：2002-08-19

Applicant: Theodore S. Moise ,  Guoqiang Xing ,  Mark Visokay ,  Justin F. Gaynor ,  Stephen R. Gilbert ,  Francis Celii ,  Scott R. Summerfelt ,  Luigi Colombo

Inventor： Theodore S. Moise ,  Guoqiang Xing ,  Mark Visokay ,  Justin F. Gaynor ,  Stephen R. Gilbert ,  Francis Celii ,  Scott R. Summerfelt ,  Luigi Colombo

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/00

CPC classification number: H01L27/11502 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/55

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract translation: 在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。

公开(公告)号：US06876021B2

公开(公告)日：2005-04-05

申请号：US10303560

申请日：2002-11-25

Applicant: J. Scott Martin ,  Scott R. Summerfelt ,  Theodore S. Moise ,  Kelly J. Taylor ,  Luigi Colombo ,  Sanjeev Aggarwal ,  Sirisha Kuchimanchi ,  K. R. Udayakumar ,  Lindsey Hall

Inventor： J. Scott Martin ,  Scott R. Summerfelt ,  Theodore S. Moise ,  Kelly J. Taylor ,  Luigi Colombo ,  Sanjeev Aggarwal ,  Sirisha Kuchimanchi ,  K. R. Udayakumar ,  Lindsey Hall

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L31/119

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55

Abstract: The present invention forms sidewall diffusion barrier layer(s) that mitigate hydrogen contamination of ferroelectric capacitors. Sidewall diffusion barrier layer(s) of the present invention are formed via a physical vapor deposition process at a low temperature. By so doing, the sidewall diffusion barrier layer(s) are substantially amorphous and provide superior protection against hydrogen diffusion than conventional and/or crystalline sidewall diffusion barrier layers.

Abstract translation: 本发明形成减轻铁电电容器的氢污染的侧壁扩散阻挡层。 本发明的侧壁扩散阻挡层通过物理气相沉积工艺在低温下形成。 通过这样做，侧壁扩散阻挡层基本上是无定形的，并提供优于常规和/或结晶侧壁扩散阻挡层的氢气扩散保护。

公开(公告)号：US06441415B1

公开(公告)日：2002-08-27

申请号：US09344580

申请日：1999-06-25

Applicant: Theodore S. Moise ,  Stephen R. Gilbert ,  Charles D. E. Lakeman ,  Scott R. Summerfelt ,  Stacey A. Yamanaka

Inventor： Theodore S. Moise ,  Stephen R. Gilbert ,  Charles D. E. Lakeman ,  Scott R. Summerfelt ,  Stacey A. Yamanaka

IPC: H01L2976

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55

Abstract: A method for simultaneously producing areas of paraelectric states and areas of ferroelectric states on a single thin film layer, thereby reducing the number of processing steps required to produce integrated chips containing both standard capacitors and non-volatile memory devices from the number of steps needed using the conventional approach. A device containing both ferroelectric capacitors and non-ferroelectric capacitors using a single thin film as the dielectric.

Abstract translation: 一种用于在单个薄膜层上同时产生顺电状态区域和铁电态区域的方法，从而减少了从所需步骤所需的步骤产生包含标准电容器和非易失性存储器件的集成芯片所需的处理步骤的数量 常规方法。 使用单个薄膜作为电介质的包含铁电电容器和非铁电电容器的装置。

公开(公告)号：US07723199B2

公开(公告)日：2010-05-25

申请号：US11669759

申请日：2007-01-31

Applicant: Yaw S. Obeng ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Sanjeev Aggarwal ,  Francis Gabriel Celii ,  Lindsey H. Hall ,  Robert Kraft ,  Theodore S. Moise

Inventor： Yaw S. Obeng ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Sanjeev Aggarwal ,  Francis Gabriel Celii ,  Lindsey H. Hall ,  Robert Kraft ,  Theodore S. Moise

IPC: H01L21/02

CPC classification number: H01L21/02071 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02263 ,  H01L21/31683 ,  H01L28/55 ,  H01L28/65

Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.

Abstract translation: 提出了制造半导体器件的方法。 一方面，该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的电极和铁电层，其中在铁电电容器的侧壁上产生导电的含贵金属的聚合物。 该方法还包括将含导电贵金属的聚合物转化为非导电金属氧化物。 转化包括从含导电贵金属的聚合物形成水溶性金属盐，并使水溶性金属盐与酸性水溶液反应，形成金属氢氧化物。 转化还包括氧化金属氢氧化物以形成非导电金属氧化物。

公开(公告)号：US07361599B2

公开(公告)日：2008-04-22

申请号：US11145663

申请日：2005-06-06

Applicant: Theodore S. Moise ,  Guoqiang Xing ,  Mark Visokay ,  Justin F. Gaynor ,  Stephen R. Gilbert ,  Francis Celii ,  Scott R. Summerfelt ,  Luigi Colombo

Inventor： Theodore S. Moise ,  Guoqiang Xing ,  Mark Visokay ,  Justin F. Gaynor ,  Stephen R. Gilbert ,  Francis Celii ,  Scott R. Summerfelt ,  Luigi Colombo

IPC: H01L21/302

CPC classification number: H01L27/11502 ,  H01L21/31116 ,  H01L21/76895 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/55

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract translation: 在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。

公开(公告)号：US07019352B2

公开(公告)日：2006-03-28

申请号：US10635994

申请日：2003-08-07

Applicant: K. R. Udayakumar ,  Martin G. Albrecht ,  Theodore S. Moise ,  Scott R. Summerfelt ,  Sarah I. Hartwig

Inventor： K. R. Udayakumar ,  Martin G. Albrecht ,  Theodore S. Moise ,  Scott R. Summerfelt ,  Sarah I. Hartwig

IPC: H01L27/01

CPC classification number: H01L21/76829 ,  H01L21/3185 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/57

Abstract: Semiconductor devices and fabrication methods are disclosed, in which one or more low silicon-hydrogen SiN barriers are provided to inhibit hydrogen diffusion into ferroelectric capacitors and into transistor gate dielectric interface areas. The barriers may be used as etch stop layers in various levels of the semiconductor device structure above and/or below the level at which the ferroelectric capacitors are formed so as to reduce the hydrogen related degradation of the switched polarization properties of the ferroelectric capacitors and to reduce negative bias temperature instability in the device transistors.

Abstract translation: 公开了半导体器件和制造方法，其中提供一个或多个低硅氢SiN栅极以阻止氢扩散到铁电电容器中并进入晶体管栅极电介质界面区域。 可以将阻挡层用作在形成强电介质电容器的电平以上和/或以下的半导体器件结构的各种级别的蚀刻停止层，以便降低铁电电容器的开关极化特性的氢相关劣化，并且 降低器件晶体管的负偏压温度不稳定性。

公开(公告)号：US07001821B2

公开(公告)日：2006-02-21

申请号：US10705039

申请日：2003-11-10

Applicant: Sanjeev Aggarwal ,  Kelly J. Taylor ,  Theodore S. Moise

Inventor： Sanjeev Aggarwal ,  Kelly J. Taylor ,  Theodore S. Moise

IPC: H01L21/20

CPC classification number: H01L27/11502 ,  H01L21/28568 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

Abstract: Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.

Abstract translation: 硬掩模和制造方法用于在半导体器件中制造铁电电容器，其中在上部电容器电极材料上方形成包括氧化铝或氧化钽锶的硬掩模，并蚀刻电容器电极和铁电层以限定铁电电容器叠层。

公开(公告)号：US06841396B2

公开(公告)日：2005-01-11

申请号：US10440697

申请日：2003-05-19

Applicant: Francis Gabriel Celii ,  K. R. Udayakumar ,  Scott R. Summerfelt ,  Theodore S. Moise

Inventor： Francis Gabriel Celii ,  K. R. Udayakumar ,  Scott R. Summerfelt ,  Theodore S. Moise

IPC: H01L21/00 ,  H01L21/20 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115

CPC classification number: H01L27/11502 ,  H01L27/11507

Abstract: A ferroelectric memory device comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereof for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and reference voltage on the second bit line.

Abstract translation: 铁电存储器件包括逻辑可编程电容参考电路。 电路适于在感测操作模式期间产生参考电压，其中参考电压包括作为一个以上存储器条件的函数的值。 存储器件还包括位线对，其中位线对的第一位线具有耦合的铁电电容器用于感测位线对，并且位线对的第二位线耦合到参考电压。 感测电路耦合到位线对，并且被配置为使用与第一位线相关联的电压和第二位线上的参考电压来检测与铁电电容器相关联的数据状态。

公开(公告)号：US06548343B1

公开(公告)日：2003-04-15

申请号：US09702985

申请日：2000-10-31

Applicant: Scott R. Summerfelt ,  Theodore S. Moise ,  Guoqiang Xing ,  Luigi Colombo ,  Tomoyuki Sakoda ,  Stephen R. Gilbert ,  Alvin L. S. Loke ,  Shawming Ma ,  Rahim Kavari ,  Laura Wills-Mirkarimi ,  Jun Amano

Inventor： Scott R. Summerfelt ,  Theodore S. Moise ,  Guoqiang Xing ,  Luigi Colombo ,  Tomoyuki Sakoda ,  Stephen R. Gilbert ,  Alvin L. S. Loke ,  Shawming Ma ,  Rahim Kavari ,  Laura Wills-Mirkarimi ,  Jun Amano

IPC: H01L218242

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/57

Abstract: An embodiment of the instant invention is a method of fabricating a ferroelectric capacitor which is situated over a structure, the method comprising the steps of: forming a bottom electrode on the structure (124 of FIG. 1), the bottom electrode having a top surface and sides; forming a capacitor dielectric (126 of FIG. 1) comprised of a ferroelectric material on the bottom electrode, the capacitor dielectric having a top surface and sides; forming a top electrode (128 and 130 of FIG. 1) on the capacitor dielectric, the top electrode having a top surface and sides, the ferroelectric capacitor is comprised of the bottom electrode, the capacitor dielectric, and the top electrode; forming a barrier layer (118 and 120 of FIG. 1) on the side of the bottom electrode, the side of the capacitor dielectric, and the side of the top electrode; forming a dielectric layer on the barrier layer and the structure, the dielectric having a top surface and a bottom surface; and performing a thermal step for a duration at a temperature between 400 and 900 C. in an ambient comprised of a gas selected from the group consisting of: argon, nitrogen, and a combination thereof, the step of performing a thermal step being performed after the step of forming the barrier layer.

Abstract translation: 本发明的一个实施例是制造位于结构上方的铁电电容器的方法，所述方法包括以下步骤：在所述结构（图1的124）上形成底电极，所述底电极具有顶表面 和边; 在底部电极上形成由铁电材料构成的电容器电介质（图1的126），电容器电介质具有顶表面和侧面; 在电容器电介质上形成顶电极（图1的128和130），顶电极具有顶表面和侧面，铁电电容器由底电极，电容器电介质和顶电极组成; 在底电极侧，电容器电介质侧和顶电极侧形成阻挡层（图1的118和120）; 在所述阻挡层和所述结构上形成电介质层，所述电介质具有顶表面和底表面; 并且在由选自氩，氮及其组合的气体组成的环境中在400-900℃的温度下进行热步骤，所述环境包括：在步骤 形成阻挡层的步骤。