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    Method of fabricating a ferroelectric memory cell
    6.
    发明授权
    Method of fabricating a ferroelectric memory cell 有权
    制造铁电存储单元的方法

    公开(公告)号：US06548343B1

    公开(公告)日：2003-04-15

    申请号：US09702985

    申请日：2000-10-31

    申请人： Scott R. Summerfelt ,  Theodore S. Moise ,  Guoqiang Xing ,  Luigi Colombo ,  Tomoyuki Sakoda ,  Stephen R. Gilbert ,  Alvin L. S. Loke ,  Shawming Ma ,  Rahim Kavari ,  Laura Wills-Mirkarimi ,  Jun Amano

    发明人： Scott R. Summerfelt ,  Theodore S. Moise ,  Guoqiang Xing ,  Luigi Colombo ,  Tomoyuki Sakoda ,  Stephen R. Gilbert ,  Alvin L. S. Loke ,  Shawming Ma ,  Rahim Kavari ,  Laura Wills-Mirkarimi ,  Jun Amano

    IPC分类号： H01L218242

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/57

    摘要： An embodiment of the instant invention is a method of fabricating a ferroelectric capacitor which is situated over a structure, the method comprising the steps of: forming a bottom electrode on the structure (124 of FIG. 1), the bottom electrode having a top surface and sides; forming a capacitor dielectric (126 of FIG. 1) comprised of a ferroelectric material on the bottom electrode, the capacitor dielectric having a top surface and sides; forming a top electrode (128 and 130 of FIG. 1) on the capacitor dielectric, the top electrode having a top surface and sides, the ferroelectric capacitor is comprised of the bottom electrode, the capacitor dielectric, and the top electrode; forming a barrier layer (118 and 120 of FIG. 1) on the side of the bottom electrode, the side of the capacitor dielectric, and the side of the top electrode; forming a dielectric layer on the barrier layer and the structure, the dielectric having a top surface and a bottom surface; and performing a thermal step for a duration at a temperature between 400 and 900 C. in an ambient comprised of a gas selected from the group consisting of: argon, nitrogen, and a combination thereof, the step of performing a thermal step being performed after the step of forming the barrier layer.

    摘要翻译： 本发明的一个实施例是制造位于结构上方的铁电电容器的方法，所述方法包括以下步骤：在所述结构（图1的124）上形成底电极，所述底电极具有顶表面 和边; 在底部电极上形成由铁电材料构成的电容器电介质（图1的126），电容器电介质具有顶表面和侧面; 在电容器电介质上形成顶电极（图1的128和130），顶电极具有顶表面和侧面，铁电电容器由底电极，电容器电介质和顶电极组成; 在底电极侧，电容器电介质侧和顶电极侧形成阻挡层（图1的118和120）; 在所述阻挡层和所述结构上形成电介质层，所述电介质具有顶表面和底表面; 并且在由选自氩，氮及其组合的气体组成的环境中在400-900℃的温度下进行热步骤，所述环境包括：在步骤 形成阻挡层的步骤。

    Ferroelectric capacitor hydrogen barriers and methods for fabricating the same
    8.
    发明授权
    Ferroelectric capacitor hydrogen barriers and methods for fabricating the same 有权
    铁电电容器氢屏障及其制造方法

    公开(公告)号：US07183602B2

    公开(公告)日：2007-02-27

    申请号：US11033224

    申请日：2005-01-11

    申请人： K. R. Udayakumar ,  Theodore S. Moise ,  Scott R. Summerfelt

    发明人： K. R. Udayakumar ,  Theodore S. Moise ,  Scott R. Summerfelt

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L27/11507 ,  H01L28/57

    摘要： Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.

    摘要翻译： 提供氢屏障和制造方法用于在半导体器件（102）中保护铁电电容器（C LIMIT）免受氢扩散，其中氮化的氧化铝（N-AlOx）形成在铁电电容器（C < 在氮化的氧化铝（N-AlOx）上形成一个或多个氮化硅层（112,117）。 还提供了氢屏障，其中在铁电电容器（CFE）上形成氧化铝（AlOx，N-AlOx），其上形成有两个或更多个氮化硅层（112,117） 氧化铝（AlOx，N-AlOx），其中第二氮化硅层（112）包括低硅氢SiN材料。

    Method for leakage reduction in fabrication of high-density FRAM arrays
    9.
    发明授权
    Method for leakage reduction in fabrication of high-density FRAM arrays 有权
    高密度FRAM阵列制造中泄漏减少的方法

    公开(公告)号：US08093070B2

    公开(公告)日：2012-01-10

    申请号：US11706722

    申请日：2007-02-15

    申请人： Francis Gabriel Celii ,  Kezhakkedath R. Udayakumar ,  Gregory B. Shinn ,  Theodore S. Moise ,  Scott R. Summerfelt

    发明人： Francis Gabriel Celii ,  Kezhakkedath R. Udayakumar ,  Gregory B. Shinn ,  Theodore S. Moise ,  Scott R. Summerfelt

    IPC分类号： H01L21/00

    CPC分类号： H01L28/75 ,  H01L27/11507 ,  H01L28/55

    摘要： A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.

    摘要翻译： 提供一种用于制造铁电电容器结构的方法，其包括在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法。 该方法包括蚀刻上电极的部分，蚀刻铁电材料，并蚀刻下电极以限定图案化的铁电电容器结构，以及蚀刻下电极扩散阻挡结构的一部分。 所述方法还包括使用第一灰化过程灰化所述图案化的铁电电容器结构，其中所述灰分包括含氧/氮/水的灰分，在所述第一灰化处理之后执行湿式清洁处理，以及使用 第二次灰化过程。

    Ferroelectric transistors using thin film semiconductor gate electrodes
    10.
    发明授权
    Ferroelectric transistors using thin film semiconductor gate electrodes 有权
    使用薄膜半导体栅电极的铁电晶体管

    公开(公告)号：US06362499B1

    公开(公告)日：2002-03-26

    申请号：US09645158

    申请日：2000-08-24

    申请人： Theodore S. Moise ,  Scott R. Summerfelt

    发明人： Theodore S. Moise ,  Scott R. Summerfelt

    IPC分类号： H01L2976

    CPC分类号： G11C29/44 ,  G11C11/223 ,  G11C2029/1208 ,  H01L21/28291 ,  H01L29/78391

    摘要： A ferroelectric structure on an integrated circuit and methods of making and using the same are disclosed, which may be used, for instance, in a high-speed, non-volatile, non-destructive readout random-access memory device. Generally, the ferroelectric structure combines a thin film ferroelectric variable resistor and a substrate (e.g. silicon) transistor, using a semiconducting film which is common to both. A field effect transistor 26 integrated into substrate 30 has a gate oxide 36 and a semiconducting gate electrode 38 with electrical connections at a first end 44 and a second end 46. Overlying gate electrode 38 is a ferroelectric thin film 40 and a conductive electrode 42. The polarization of ferroelectric thin film 40 is set by applying an appropriate voltage between gate electrode 38 and conductive electrode 42. The polarization of ferroelectric thin film 40 may be subsequently determined by applying a read voltage to 42 and 44, thus causing a voltage V2 to appear at 46 which is determined by the polarization of the ferroelectric variable resistor formed by 38 and 40. Since 38 also forms the gate electrode for field effect transistor 26, the magnitude of V2 affects the magnitude of current I2. Thus I2 is effectively an amplified signal related to the ferroelectric variable resistance which may be read without perturbing the polarization of ferroelectric thin film 40.

    摘要翻译： 公开了集成电路中的铁电结构及其制造和使用的方法，其可以用于例如高速，非易失性，非破坏性读出随机存取存储器件中。 通常，铁电结构使用两者共同的半导体膜组合薄膜铁电可变电阻器和衬底（例如硅）晶体管。 集成到基板30中的场效应晶体管26具有在第一端44和第二端46具有电连接的栅极氧化物36和半导体栅电极38.叠层栅电极38是铁电薄膜40和导电电极42。 通过在栅电极38和导电电极42之间施加适当的电压来设定铁电薄膜40的极化。随后可以通过将读电压施加到42和44来确定铁电薄膜40的极化，从而使电压V2 出现在46处，其由38和40形成的铁电可变电阻器的极化决定。由于38还形成场效应晶体管26的栅电极，因此V2的大小影响电流I2的大小。 因此，I2实际上是与铁电可变电阻相关的放大信号，其可以在不扰乱铁电薄膜40的极化的情况下读取。