公开(公告)号：US08354730B2

公开(公告)日：2013-01-15

申请号：US11997436

申请日：2006-08-25

申请人： Satoshi Moriya ,  Toshio Saito ,  Goichi Yokoyama ,  Tsuyoshi Fujiwara ,  Hidenori Sato ,  Nobuaki Miyakawa

发明人： Satoshi Moriya ,  Toshio Saito ,  Goichi Yokoyama ,  Tsuyoshi Fujiwara ,  Hidenori Sato ,  Nobuaki Miyakawa

IPC分类号： H01L21/70

CPC分类号： H01L21/76898 ,  H01L21/2007 ,  H01L21/76232 ,  H01L21/8221 ,  H01L23/481 ,  H01L24/94 ,  H01L2224/2518 ,  H01L2924/01004 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/00

摘要： A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS•FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved.

摘要翻译： 提供了通过将形成在各个半导体衬底的半导体芯片上的多个半导体衬底和电连接集成电路粘合在一起而获得所需集成电路的结构，并且穿透电极穿透每个半导体衬底的主表面和后表面 分离基板和分离穿透电极的穿透分离部分。 因此，在半导体衬底上形成用于形成穿透分离部分的绝缘沟槽部分之后，形成MIS·FET，然后形成用于形成穿透电极的导电沟槽部分。 因此，可以提高具有三维结构的半导体器件的元件特性。

公开(公告)号：US08212649B2

公开(公告)日：2012-07-03

申请号：US13238056

申请日：2011-09-21

申请人： Tsuyoshi Fujiwara ,  Toshinori Imai ,  Kenichi Takeda ,  Hiromi Shimamoto

发明人： Tsuyoshi Fujiwara ,  Toshinori Imai ,  Kenichi Takeda ,  Hiromi Shimamoto

IPC分类号： H01C1/12

CPC分类号： H01L23/5228 ,  H01L27/0688 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.

摘要翻译： 根据本发明的半导体器件包括：形成在金属电阻器元件的下表面上的下表面的氧化防止绝缘膜; 形成在所述金属电阻元件的上表面上的上表面氧化防止绝缘膜; 以及侧面氧化防止绝缘膜，其仅在金属电阻元件的侧面附近形成，在与下表面的氧化防止绝缘膜分离的工序中沉积在晶片的整个表面上，进行各向异性蚀刻 表面氧化防止绝缘膜。 根据本发明，可以防止由于金属电阻元件的氧化引起的电阻值的增加，并且还可以防止金属布线层之间的寄生电容的增加，而不会使制造工艺复杂化。

公开(公告)号：US20120159859A1

公开(公告)日：2012-06-28

申请号：US13413142

申请日：2012-03-06

申请人： Chikara Yamashita ,  Akihiro Terai ,  Hiromichi Torihata ,  Tsuyoshi Fujiwara

发明人： Chikara Yamashita ,  Akihiro Terai ,  Hiromichi Torihata ,  Tsuyoshi Fujiwara

IPC分类号： B60J10/04

CPC分类号： B60J5/0402 ,  B60J10/21

摘要： A center-channel protector for a vehicle sash door is arranged between a main sash and a center channel. A body of the protector has an H-shaped upper-end surface which is compatible to cover the upper end of the center channel. The body integrally includes a pair of branch covering portions corresponding to a pair of branch portions constituting the center channel and a middle covering portion disposed between the branch covering portions so as to connect the both branch covering portions therewith. An engaging portion is provided with the body and is mechanically engaged, in a direction intersecting a vertical direction, with an engaged portion which is provided with a center channel side. In collaboration with the engaged portion, the engaging portion constitutes a fastening mechanism by which the protector is fastened on the center channel.

摘要翻译： 主窗框和中央通道之间布置有用于车窗扇门的中心通道保护器。 保护器的主体具有H形的上表面，其兼容以覆盖中心通道的上端。 主体一体地包括一对分支覆盖部分，对应于构成中心通道的一对分支部分，以及设置在分支覆盖部分之间的中间覆盖部分，以便连接两个分支覆盖部分。 接合部设置有主体并且在与垂直方向相交的方向上机械地接合设置有中心通道侧的接合部。 与接合部一起，接合部分构成紧固机构，保护器通过该紧固机构紧固在中心通道上。

公开(公告)号：US08040214B2

公开(公告)日：2011-10-18

申请号：US12481384

申请日：2009-06-09

申请人： Tsuyoshi Fujiwara ,  Toshinori Imai ,  Kenichi Takeda ,  Hiromi Shimamoto

发明人： Tsuyoshi Fujiwara ,  Toshinori Imai ,  Kenichi Takeda ,  Hiromi Shimamoto

IPC分类号： H01C1/12

CPC分类号： H01L23/5228 ,  H01L27/0688 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.

摘要翻译： 根据本发明的半导体器件包括：形成在金属电阻器元件的下表面上的下表面的氧化防止绝缘膜; 形成在所述金属电阻元件的上表面上的上表面氧化防止绝缘膜; 以及侧面氧化防止绝缘膜，其仅在金属电阻元件的侧面附近形成，在与下表面的氧化防止绝缘膜分离的工序中沉积在晶片的整个表面上，进行各向异性蚀刻 表面氧化防止绝缘膜。 根据本发明，可以防止由于金属电阻元件的氧化引起的电阻值的增加，并且还可以防止金属布线层之间的寄生电容的增加，而不会使制造工艺复杂化。

公开(公告)号：US20100181647A1

公开(公告)日：2010-07-22

申请号：US12750402

申请日：2010-03-30

申请人： Toshinori IMAI ,  Tsuyoshi Fujiwara ,  Hiroshi Ashihara ,  Akira Ootaguro ,  Yoshihiro Kawasaki

发明人： Toshinori IMAI ,  Tsuyoshi Fujiwara ,  Hiroshi Ashihara ,  Akira Ootaguro ,  Yoshihiro Kawasaki

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

摘要： In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.

摘要翻译： 在本发明中，电容元件的下电极的上阻挡膜和与其形成的相同层中的金属互连层的上阻挡膜的膜厚比其他的上阻挡膜的膜厚更厚 金属互连层。 此外，在本发明中，电容元件的下电极的上阻挡膜的膜厚控制在110nm以上，更优选为160nm以上。 不会发生由于上阻挡膜中的裂纹引起的电容电介质膜的电介质电压的降低，并且可以使电容电介质膜的沉积温度更高，使得具有高性能和高的MIM电容器的半导体器件 可以实现电容，其中电容电介质膜的介电电压得到改善。

公开(公告)号：US20070048543A1

公开(公告)日：2007-03-01

申请号：US10554832

申请日：2004-10-19

申请人： Tsuyoshi Fujiwara ,  Yoshihiro Manabe ,  Taishi Ogawa ,  Yoshiaki Meguro

发明人： Tsuyoshi Fujiwara ,  Yoshihiro Manabe ,  Taishi Ogawa ,  Yoshiaki Meguro

IPC分类号： B21D5/08

CPC分类号： B60J5/0402 ,  B60R13/04 ,  Y10T29/49622 ,  Y10T29/49915 ,  Y10T428/12354

摘要： To use the same sash material for producing two types of a vehicular door sash, a lower-cost type provided with no sash molding, and a luxury type provided with sash molding produced through additional roll molding means to reduce the width of its flange portion. The additional roll molding means (D) performed by a plurality of rollers (D1, D2, D3) includes a crushing step that crushes a space formed on the back surface of the flange portion 3 under pressure, and a bending step that bends an end portion 12 of the crushed flange portion 3 at the side of the groove portion 1 upward.

摘要翻译： 为了使用相同的窗框材料来生产两种类型的车门扇，较低成本的类型没有窗框模制，而豪华型设置有通过附加的卷筒成型装置产生的窗扇模制，以减小其凸缘部分的宽度。 通过多个辊（D 1，D 2，D 3）进行的附加的辊成型装置（D）包括在压力下破碎形成在凸缘部3的后表面上的空间的破碎步骤，以及弯曲步骤 将破碎的凸缘部3的在槽部1侧的端部12向上弯曲。

公开(公告)号：US20070018327A1

公开(公告)日：2007-01-25

申请号：US11529481

申请日：2006-09-29

申请人： Tsuyoshi Fujiwara ,  Masahiro Ushiyama ,  Katsuhiko Ichinose ,  Naohumi Ohashi ,  Tetsuo Saito

发明人： Tsuyoshi Fujiwara ,  Masahiro Ushiyama ,  Katsuhiko Ichinose ,  Naohumi Ohashi ,  Tetsuo Saito

IPC分类号： H01L23/52

CPC分类号： H01L21/76834 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/76816 ,  H01L21/76828 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823828 ,  H01L21/823871 ,  H01L24/11 ,  H01L27/0629 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10888 ,  H01L27/10894 ,  H01L28/24 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.

摘要翻译： 在制造具有高性能和高可靠性的半导体器件中，在400℃的衬底温度下形成用于自对准的氮化硅膜17，该膜形成为覆盖MISFET的栅电极。 以上，使用包括甲硅烷和氮的原料气体的等离子体CVD。 构成钝化膜的氮化硅膜44通过使用包括甲硅烷，氨和氮的原料气体的等离子体CVD在基板温度约350℃下形成。 氮化硅膜17中所含的氢含量小于氮化硅膜44中所含的氢含量，可以抑制从氮化硅膜17释放氢。

公开(公告)号：US07163886B2

公开(公告)日：2007-01-16

申请号：US10917289

申请日：2004-08-13

申请人： Tsuyoshi Fujiwara ,  Masahiro Ushiyama ,  Katsuhiko Ichinose ,  Naohumi Ohashi ,  Tetsuo Saito

发明人： Tsuyoshi Fujiwara ,  Masahiro Ushiyama ,  Katsuhiko Ichinose ,  Naohumi Ohashi ,  Tetsuo Saito

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/76816 ,  H01L21/76828 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823828 ,  H01L21/823871 ,  H01L24/11 ,  H01L27/0629 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10888 ,  H01L27/10894 ,  H01L28/24 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.

公开(公告)号：US07042095B2

公开(公告)日：2006-05-09

申请号：US10387504

申请日：2003-03-14

申请人： Junji Noguchi ,  Tsuyoshi Fujiwara

发明人： Junji Noguchi ,  Tsuyoshi Fujiwara

IPC分类号： H01L21/88 ,  H01L23/48

CPC分类号： H01L23/53295 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S257/914 ,  H01L2924/00

摘要： Provided are a semiconductor device comprising a semiconductor substrate, a first insulating film formed thereover, interconnects formed over the first insulating film and having copper as a main component, a second insulating film formed over the upper surface and side surfaces of each of the interconnects and over the first insulating film and having a function of suppressing or preventing copper diffusion, and a third insulating film formed over the second insulating film and having a dielectric constant lower than that of the second insulating film; and a method of manufacturing the semiconductor device. This invention makes it possible to improve dielectric breakdown strength between copper interconnects and reduce capacitance between the copper interconnects.

摘要翻译： 提供了一种半导体器件，包括半导体衬底，形成在其上的第一绝缘膜，形成在第一绝缘膜上并具有铜作为主要部件的互连，形成在每个互连的上表面和侧表面上的第二绝缘膜， 超过第一绝缘膜并具有抑制或防止铜扩散的功能;以及第三绝缘膜，形成在第二绝缘膜上并具有低于第二绝缘膜的介电常数的介电常数; 以及半导体器件的制造方法。 本发明使得可以提高铜互连之间的介电击穿强度并降低铜互连之间的电容。

公开(公告)号：US4245245A

公开(公告)日：1981-01-13

申请号：US654721

申请日：1976-02-02

申请人： Katsuaki Matsumoto ,  Yoshifumi Saeki ,  Osamu Tazawa ,  Minoru Kosaka ,  Masaki Saito ,  Hiroki Uemura ,  Tetuo Kanazashi ,  Seiji Hashimoto ,  Tsuyoshi Fujiwara ,  Tsutomu Fukui ,  Saburo Takaoka ,  Tsutomu Suzuki ,  Shozo Nakamuta ,  Toshihiko Hosaka ,  Kuniaki Shiratori ,  Youichiro Tsuda ,  Takashi Morii ,  Sumitaka Matsumura ,  Morihisa Oka

发明人： Katsuaki Matsumoto ,  Yoshifumi Saeki ,  Osamu Tazawa ,  Minoru Kosaka ,  Masaki Saito ,  Hiroki Uemura ,  Tetuo Kanazashi ,  Seiji Hashimoto ,  Tsuyoshi Fujiwara ,  Tsutomu Fukui ,  Saburo Takaoka ,  Tsutomu Suzuki ,  Shozo Nakamuta ,  Toshihiko Hosaka ,  Kuniaki Shiratori ,  Youichiro Tsuda ,  Takashi Morii ,  Sumitaka Matsumura ,  Morihisa Oka

IPC分类号： H04N7/167 ,  H04N7/171 ,  H04N7/173 ,  H04N7/16 ,  H04N7/00

CPC分类号： H04N7/17309 ,  H04N7/17363 ,  H04N2007/17372

摘要： A two-way CATV system having a substantial number of terminals incorporates a central processor and transmitter system which continually interrogates the terminals at high speed, monitoring changes of usage of premium programs and other data while also permitting central control of access to restricted premium programs. For inexpensive but reliable intercommunication, short, fixed word length digital messages are frequency multiplexed onto the cable in both upstream and downstream directions, and subscriber groups are controllably selected in turn, with each subscriber being scanned in what may be an arbitrary order by transmission of unique private messages which are recognized at the terminal and in response to which previously prepared fixed length messages are immediately transmitted in return. By employing both upstream and downstream messages which are initiated by a series of synchronizing bits and non-ambiguously related subsequent data sequences, and by the provision of means to initiate both downstream and upstream messages of short length without delay, rapid but reliable data interchange is effected despite differences in transmission and response times with different subscribers. Concurrently, terminal status and various special conditions including security alarms are remotely processed at each terminal, and short upstream messages are assembled containing priority selected data to be transmitted in response to an interrogation. The system incorporates additional means for monitoring power status, program selection and authorization and other operating conditions at each terminal effectively to provide accurate and reliable accounting information while preventing unauthorized or improper usage of restricted premium programs.

摘要翻译： 具有大量终端的双向CATV系统包括中央处理器和发射机系统，其以高速度连续询问终端，监视高级节目和其他数据的使用的改变，同时还允许对受限优惠节目的访问的中央控制。 对于廉价但可靠的互通，短，固定字长数字消息在上行和下行两个方向上被频率复用到电缆上，并且用户组可以依次可控地选择，每个用户以任意顺序扫描可以通过传输 在终端被识别并且响应于先前准备好的固定长度的消息被立即发送的唯一私人消息。 通过采用由一系列同步位和非相关相关的后续数据序列发起的上行和下行消息，并且通过提供无延迟地启动短长度的下行和上行消息的装置，快速但可靠的数据交换是 尽管与不同用户的传输和响应时间有差异。 同时，终端状态和包括安全警报在内的各种特殊条件在每个终端进行远程处理，并且组合短的上游消息，其中包含响应于询问要发送的优先选择数据。 该系统包括用于监控每个终端的电源状态，程序选择和授权以及其他操作条件的其他手段，有效地提供准确可靠的会计信息，同时防止未经授权或不正确使用限制性溢价程序。