公开(公告)号：US10927000B2

公开(公告)日：2021-02-23

申请号：US15295997

申请日：2016-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Che Chen ,  Te-Yuan Wu ,  Chia-Huei Lin ,  Hui-Min Wu ,  Kun-Che Hsieh ,  Kuan-Yu Wang ,  Chung-Yi Chiu

IPC: B81B3/00 ,  B81C1/00

Abstract: A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.

公开(公告)号：US08981501B2

公开(公告)日：2015-03-17

申请号：US13870706

申请日：2013-04-25

Applicant: United Microelectronics Corp.

Inventor： Meng-Jia Lin ,  Chang-Sheng Hsu ,  Kuo-Hsiung Huang ,  Wei-Hua Fang ,  Shou-Wei Hsieh ,  Te-Yuan Wu ,  Chia-Huei Lin

IPC: H01L29/84 ,  H01L21/311 ,  H01L23/48 ,  B81C1/00 ,  H01L27/06

CPC classification number: H01L21/31116 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0617 ,  H01L2924/0002 ,  H04R2201/003 ,  H01L2924/00

Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.

Abstract translation: 公开了一种形成半导体器件的方法。 提供了具有至少一个MOS器件，至少一个金属互连和至少一个MOS器件的衬底，该MOS器件形成在其第一表面上。 执行第一各向异性蚀刻工艺以从衬底的第二表面去除衬底的一部分，从而在衬底中形成多个通孔，其中第二表面与第一表面相对。 执行第二各向异性蚀刻工艺以从衬底的第二表面移除衬底的另一部分，从而在衬底中形成空腔，其中剩余的通孔位于腔的下方。 对空腔和剩余的通孔进行各向同性蚀刻工艺。

公开(公告)号：US20140319693A1

公开(公告)日：2014-10-30

申请号：US13870706

申请日：2013-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Meng-Jia Lin ,  Chang-Sheng Hsu ,  Kuo-Hsiung Huang ,  Wei-Hua Fang ,  Shou-Wei Hsieh ,  Te-Yuan Wu ,  Chia-Huei Lin

IPC: H01L21/311 ,  H01L23/48

CPC classification number: H01L21/31116 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0617 ,  H01L2924/0002 ,  H04R2201/003 ,  H01L2924/00

Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.

Abstract translation: 公开了一种形成半导体器件的方法。 提供了具有至少一个MOS器件，至少一个金属互连和至少一个MOS器件的衬底，该MOS器件形成在其第一表面上。 执行第一各向异性蚀刻工艺以从衬底的第二表面去除衬底的一部分，从而在衬底中形成多个通孔，其中第二表面与第一表面相对。 执行第二各向异性蚀刻工艺以从衬底的第二表面移除衬底的另一部分，从而在衬底中形成空腔，其中剩余的通孔位于腔的下方。 对空腔和剩余的通孔进行各向同性蚀刻工艺。

公开(公告)号：US12131976B2

公开(公告)日：2024-10-29

申请号：US17037542

申请日：2020-09-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/36 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L23/485 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L23/3677 ,  H01L21/76898 ,  H01L23/3735 ,  H01L23/481 ,  H01L23/485 ,  H01L24/08 ,  H01L24/32 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2224/32225

Abstract: A semiconductor structure with a heat dissipation structure includes a first device wafer includes a front side and a back side. A first transistor is disposed on the front side. The first transistor includes a first gate structure disposed on the front side. Two first source/drain doping regions are embedded within the first device wafer at two side of the first gate structure. A channel region is disposed between the two first source/drain doping regions and embedded within the first device wafer. A first dummy metal structure contacts the back side of the first device wafer, and overlaps the channel region.

公开(公告)号：US20240162093A1

公开(公告)日：2024-05-16

申请号：US18080688

申请日：2022-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chu-Chun Chang ,  Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device includes first providing a substrate having a core region, a LNA region, a I/O region, and a PA region, forming a first gate structure on the LNA region, a second gate structure on the PA region, a third gate structure on the core region, and a fourth gate structure on the I/O region, forming an interlayer dielectric (ILD) layer on the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure, and then forming a first hard mask on the first gate structure and a second hard mask on the second gate structure. Preferably, a width of the first hard mask is greater than a width of the first gate structure.

公开(公告)号：US11848253B2

公开(公告)日：2023-12-19

申请号：US17521805

申请日：2021-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Pin Hsu ,  Chih-Jung Wang ,  Chu-Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Purakh Raj Verma

IPC: H01L23/482 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L23/4821 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/7682 ,  H01L21/76243 ,  H01L23/485

Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.

公开(公告)号：US20230230938A1

公开(公告)日：2023-07-20

申请号：US18123317

申请日：2023-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/58 ,  H01L21/71 ,  H01L21/56

CPC classification number: H01L23/585 ,  H01L21/71 ,  H01L21/56

Abstract: A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

公开(公告)号：US11637080B2

公开(公告)日：2023-04-25

申请号：US17402633

申请日：2021-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

Abstract: A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

公开(公告)号：US11521891B2

公开(公告)日：2022-12-06

申请号：US17340075

申请日：2021-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L21/762 ,  H01L21/761 ,  H01L21/311 ,  H01L21/763 ,  H01L21/764 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/10

Abstract: A semiconductor device includes: a metal-oxide semiconductor (MOS) transistor on a substrate; a deep trench isolation structure in the substrate and around the MOS transistor; and a trap rich isolation structure in the substrate and surrounding the deep trench isolation structure. Preferably, the deep trench isolation structure includes a liner in the substrate and an insulating layer on the liner, in which the top surfaces of the liner and the insulating layer are coplanar. The trap rich isolation structure is made of undoped polysilicon and the trap rich isolation structure includes a ring surrounding the deep trench isolation structure according to a top view.

公开(公告)号：US20210296159A1

公开(公告)日：2021-09-23

申请号：US17340075

申请日：2021-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L21/762 ,  H01L21/761 ,  H01L21/311 ,  H01L21/763 ,  H01L21/764 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes: a metal-oxide semiconductor (MOS) transistor on a substrate; a deep trench isolation structure in the substrate and around the MOS transistor; and a trap rich isolation structure in the substrate and surrounding the deep trench isolation structure. Preferably, the deep trench isolation structure includes a liner in the substrate and an insulating layer on the liner, in which the top surfaces of the liner and the insulating layer are coplanar. The trap rich isolation structure is made of undoped polysilicon and the trap rich isolation structure includes a ring surrounding the deep trench isolation structure according to a top view.