公开(公告)号：US10685964B2

公开(公告)日：2020-06-16

申请号：US16028364

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chieh Tsai ,  Pin-Hong Chen ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L27/108

Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.

公开(公告)号：US10199228B2

公开(公告)日：2019-02-05

申请号：US15479292

申请日：2017-04-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Nien-Ting Ho ,  Chien-Hao Chen ,  Hsin-Fu Huang ,  Chi-Yuan Sun ,  Wei-Yu Chen ,  Min-Chuan Tsai ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC: H01L21/76 ,  H01L21/28 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

Abstract: A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.

公开(公告)号：US20170323950A1

公开(公告)日：2017-11-09

申请号：US15656778

申请日：2017-07-21

Applicant: United Microelectronics Corp.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia-Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Min-Chuan Tsai ,  Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/285 ,  H01L29/267 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/267 ,  H01L29/45 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

公开(公告)号：US09558996B2

公开(公告)日：2017-01-31

申请号：US14480648

申请日：2014-09-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Mao Hsu ,  Hsin-Fu Huang ,  Min-Chuan Tsai ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chin-Fu Lin ,  Jing-Gang Li ,  Min-Hsien Chen ,  Jian-Hong Su

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/28 ,  H01L29/66 ,  H01L23/522 ,  H01L23/532 ,  H01L29/51

CPC classification number: H01L21/76846 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method.

Abstract translation: 公开了一种用金属层填充沟槽的方法。 提供具有多个支撑销的沉积装置。 设置有基板和介电层。 电介质层具有沟槽。 在将基板放置在支撑销上以在沟槽中形成金属层之后立即执行第一沉积工艺，其中在第一沉积工艺期间，基板的温度逐渐增加以达到预定温度。 当基板的温度达到预定温度时，执行第二沉积工艺以用金属层完全填充沟槽。 本发明还提供了具有大于1的反射率的铝层的半导体器件，其中通过使用该方法形成半导体器件。

公开(公告)号：US20160336270A1

公开(公告)日：2016-11-17

申请号：US14710583

申请日：2015-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Shu Min Huang ,  Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

Abstract translation: 用于形成插头的半导体工艺包括以下步骤。 在基板上形成具有凹部的电介质层。 形成钛层以保形地覆盖凹部。 第一氮化钛层被形成为保形地覆盖钛层，由此第一氮化钛层具有第一侧壁部分。 第一氮化钛层的第一侧壁部分被拉回，从而形成第二侧壁部分。 形成第二氮化钛层以覆盖凹部。 此外，还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US20150380512A1

公开(公告)日：2015-12-31

申请号：US14848362

申请日：2015-09-09

Applicant: United Microelectronics Corp.

Inventor： Chan-Lon Yang ,  Chi-Mao Hsu ,  Chun-Yuan Wu ,  Tzyy-Ming Cheng ,  Shih-Fang Tzou ,  Chin-Fu Lin ,  Hsin-Fu Huang ,  Min-Chuan Tsai

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.

Abstract translation: 一种金属栅极结构的制造方法，其特征在于，具备在其上依次形成有高K栅极电介质层和底部阻挡层的基板，在基板上形成功函数金属层，对功函数金属层进行退火处理 原位。

公开(公告)号：US09018086B2

公开(公告)日：2015-04-28

申请号：US14105198

申请日：2013-12-13

Applicant: United Microelectronics Corp.

Inventor： Chi-Mao Hsu ,  Hsin-Fu Huang ,  Chin-Fu Lin ,  Min-Chuan Tsai ,  Wei-Yu Chen ,  Chien-Hao Chen

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L29/76 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28026 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.

Abstract translation: 本发明提供一种形成具有金属栅极的半导体器件的方法。 提供基板，并且在其上形成栅极电介质和功函数金属层，其中功函数金属层在栅极电介质层上。 然后，在功函数金属层上形成顶部阻挡层。 形成顶部阻挡层的步骤包括增加顶部阻挡层中边界保护材料的浓度。 最后，在顶部阻挡层上形成金属层。 本发明还提供一种具有金属栅极的半导体器件。

公开(公告)号：US20150061042A1

公开(公告)日：2015-03-05

申请号：US14016234

申请日：2013-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsun-Min Cheng ,  Nien-Ting Ho ,  Chien-Hao Chen ,  Ching-Yun Chang ,  Hsin-Fu Huang ,  Min-Chuan Tsai ,  Chi-Yuan Sun ,  Chi-Mao Hsu

IPC: H01L29/49 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/285

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A metal gate structure is provided. The metal gate structure includes a semiconductor substrate, a gate dielectric layer, a multi-layered P-type work function layer and a conductive metal layer. The gate dielectric layer is disposed on the semiconductor substrate. The multi-layered P-type work function layer is disposed on the gate dielectric layer, and the multi-layered P-type work function layer includes at least a crystalline P-type work function layer and at least an amorphous P-type work function layer. Furthermore, the conductive metal layer is disposed on the multi-layered P-type work function layer.

Abstract translation: 提供了金属栅极结构。 金属栅极结构包括半导体衬底，栅极电介质层，多层P型功函数层和导电金属层。 栅极电介质层设置在半导体衬底上。 多层P型功函数层设置在栅极电介质层上，多层P型功函数层至少包含结晶P型功函数层和至少一非晶P型功函数层 层。 此外，导电性金属层设置在多层P型功函数层上。

公开(公告)号：US20240237550A1

公开(公告)日：2024-07-11

申请号：US18611753

申请日：2024-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Yen-Tsai Yi ,  Hsiang-Wen Ke

IPC: H10N50/80 ,  G11C11/16 ,  H01F10/32 ,  H01F41/32 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10N50/01 ,  H01F10/3254 ,  H01F41/32 ,  H10N50/85

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a
MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

公开(公告)号：US11165019B2

公开(公告)日：2021-11-02

申请号：US16576784

申请日：2019-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Min Chou ,  Kuo-Chih Lai ,  Wei-Ming Hsiao ,  Hui-Ting Lin ,  Szu-Yao Yu ,  Nien-Ting Ho ,  Hsin-Fu Huang ,  Chin-Fu Lin

IPC: H01L45/00

Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.