公开(公告)号：US09236471B2

公开(公告)日：2016-01-12

申请号：US14253365

申请日：2014-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Ke-Feng Lin ,  Shu-Wen Lin ,  Kun-Huang Yu ,  Chih-Chung Wang ,  Te-Yuan Wu

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.

Abstract translation: 半导体结构包括具有第一导电类型的衬底; 在衬底中形成有第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，其包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分穿透所述隔离。 导电插头的第二部分的底表面被隔离层覆盖。

公开(公告)号：US20150079754A1

公开(公告)日：2015-03-19

申请号：US14548248

申请日：2014-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chung Wang ,  Wei-Lun Hsu ,  Shan-Shi Huang ,  Ke-Feng Lin ,  Te-Yuan Wu

IPC: H01L29/66 ,  H01L21/033 ,  H01L29/08 ,  H01L21/266 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/66681 ,  H01L21/0334 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7816

Abstract: The present invention provides a method of fabricating a HV MOS transistor device, including forming a deep well in a substrate, and the deep well; forming a first doped region in the deep well, and the first doped region, wherein a doping concentration of the first doped region and a doping concentration of the deep well in at least one electric field concentration region has a first ratio, the doping concentration of the first doped region and the doping concentration of the deep well outside the electric field concentration region has a second ratio, and the first ratio is greater than the second ratio; and forming a high voltage well in the substrate, and forming a second doped region and a third doped region respectively in the deep well and in the high voltage well.

Abstract translation: 本发明提供一种制造HV MOS晶体管器件的方法，包括在衬底和深阱中形成深阱; 在所述深阱中形成第一掺杂区域和所述第一掺杂区域，其中所述第一掺杂区域的掺杂浓度和所述深阱在至少一个电场浓度区域中的掺杂浓度具有第一比率，所述第一掺杂区域的掺杂浓度 第一掺杂区域和电场浓度区外的深阱的掺杂浓度具有第二比例，第一比值大于第二比例; 以及在所述衬底中形成高电压阱，以及分别在所述深阱和所述高电压阱中形成第二掺杂区和第三掺杂区。

公开(公告)号：US08921972B2

公开(公告)日：2014-12-30

申请号：US13896289

申请日：2013-05-16

Applicant: United Microelectronics Corp.

Inventor： Ming-Shun Hsu ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L21/70 ,  H01L29/78 ,  H01L27/092 ,  H01L27/085 ,  H01L27/088

CPC classification number: H01L29/7816 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/085 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878

Abstract: A high voltage metal-oxide-semiconductor (HV MOS) transistor device includes a substrate, a drifting region formed in the substrate, a plurality of isolation structures formed in the drift region and spaced apart from each other by the drift region, a plurality of doped islands respectively formed in the isolation structures, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective two sides of the gate. The gate covers a portion of each isolation structure. The drift region, the source region, and the drain region include a first conductivity type, the doped islands include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 高压金属氧化物半导体（HV MOS）晶体管器件包括衬底，形成在衬底中的漂移区域，形成在漂移区域中并由漂移区域彼此分开的多个隔离结构，多个 分别形成在隔离结构中的掺杂岛，形成在衬底上的栅极，以及在栅极的相应两侧形成在衬底中的源极区和漏极区。 门覆盖每个隔离结构的一部分。 漂移区域，源区域和漏极区域包括第一导电类型，掺杂岛包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。

公开(公告)号：US20140091369A1

公开(公告)日：2014-04-03

申请号：US13629609

申请日：2012-09-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/7816

Abstract: A HV MOS transistor device is provided. The HV MOS transistor device includes a substrate comprising at least an insulating region formed thereon, a gate positioned on the substrate and covering a portion of the insulating region, a drain region and a source region formed at respective sides of the gate in the substrate, and a first implant region formed under the insulating region. The substrate comprises a first conductivity type, the drain, the source, and the first implant region comprise a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 提供HV MOS晶体管器件。 HV MOS晶体管器件包括至少包括形成在其上的绝缘区域的衬底，位于衬底上并覆盖绝缘区域的一部分的栅极，形成在衬底中的栅极的各个侧面处的漏极区域和源极区域， 以及形成在所述绝缘区域下方的第一注入区域。 衬底包括第一导电类型，漏极，源极和第一注入区域包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。

公开(公告)号：US10985071B1

公开(公告)日：2021-04-20

申请号：US16667921

申请日：2019-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Cheng Yang ,  Yi-Han Su ,  Sheng-Chen Chung ,  Chen-An Kuo ,  Chun-Lin Chen ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L21/8234 ,  H01L21/8249 ,  H01L21/8238 ,  H01L21/28

Abstract: A gate oxide forming process includes the following steps. A substrate including a first area and a second area is provided. A first oxide layer, a silicon containing cap layer and a second oxide layer on the substrate of the first area and the second area are sequentially and blanketly formed. The silicon containing cap layer and the second oxide layer in the first area are removed. An oxidation process is performed to oxidize the silicon containing cap layer and a gate oxide layer is formed in the second area.

公开(公告)号：US10535734B2

公开(公告)日：2020-01-14

申请号：US16460813

申请日：2019-07-02

Applicant: United Microelectronics Corp.

Inventor： Shin-Hung Li ,  Kuan-Chuan Chen ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L21/8234 ,  H01L29/08 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L27/06

Abstract: Method for fabricating semiconductor device, including semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

公开(公告)号：US20190326398A1

公开(公告)日：2019-10-24

申请号：US16460813

申请日：2019-07-02

Applicant: United Microelectronics Corp.

Inventor： SHIN-HUNG LI ,  Kuan-Chuan Chen ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/08 ,  H01L21/762 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

Abstract: Method for fabricating semiconductor device, including semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

公开(公告)号：US10276652B1

公开(公告)日：2019-04-30

申请号：US16005652

申请日：2018-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Hua Yang ,  Ke-Feng Lin ,  Ming-Tsung Lee ,  Shih-Teng Huang ,  Chih-Chung Wang ,  Chiu-Te Lee ,  Shu-Wen Lin

IPC: H01L29/06 ,  H01L29/872

Abstract: A schottky diode includes a schottky junction, an ohmic junction, a first isolation structure and a plurality of doped regions. The schottky junction includes a first well in a substrate and a first electrode contacting the first well. The ohmic junction includes a junction region in the first well and a second electrode contacting the junction region. The first isolation structure is disposed in the substrate and separates the schottky junction from the ohmic junction. The doped regions are located in the first well and under the schottky junction, wherein the doped regions separating from each other constitute a top-view profile of concentric circles.

公开(公告)号：US20180097104A1

公开(公告)日：2018-04-05

申请号：US15820467

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Kai-Kuen Chang ,  Ping-Hung Chiang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7823 ,  H01L21/033 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66681

Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

公开(公告)号：US09577069B1

公开(公告)日：2017-02-21

申请号：US15136982

申请日：2016-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chieh Pu ,  Ping-Hung Chiang ,  Chang-Po Hsiung ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang ,  Kuan-Lin Liu

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/308 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L21/02238 ,  H01L21/28123 ,  H01L21/3081 ,  H01L29/0649 ,  H01L29/66575 ,  H01L29/66681

Abstract: A method of fabricating a MOS device is disclosed. A substrate having an active area (AA) silicon portion and shallow trench isolation (STI) region surrounding the active area is provided. A hard mask is formed on the substrate. A portion of the hard mask is removed to form an opening on the AA silicon portion. The opening exposes an edge of the STI region. The AA silicon portion is recessed through the opening to a predetermined depth to form a silicon spacer along a sidewall of the STI region in a self-aligned manner. An oxidation process is performed to oxidize the AA silicon portion and the silicon spacer to form a gate oxide layer.

Abstract translation: 公开了制造MOS器件的方法。 提供了具有有源区（AA）硅部分和围绕有源区的浅沟槽隔离（STI）区的衬底。 在基板上形成硬掩模。 去除硬掩模的一部分以在AA硅部分上形成开口。 开口露出STI区域的边缘。 AA硅部分通过开口凹入预定深度，以自对准的方式沿着STI区域的侧壁形成硅间隔物。 进行氧化处理以氧化AA硅部分和硅间隔物以形成栅极氧化物层。