公开(公告)号：US08782572B1

公开(公告)日：2014-07-15

申请号：US13802587

申请日：2013-03-13

Applicant: United Microelectronics Corp.

Inventor： Sheng-Yuan Huang ,  Chia-Wei Huang ,  Ming-Jui Chen

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F1/70

Abstract: A method of optical proximity correction (OPC) includes the following steps. First, a layout pattern is provided to a computer system. Subsequently, the layout pattern is classified into a first sub-layout pattern and a second sub-layout pattern. Then, an OPC calculation based on a first OPC model is performed on the first sub-layout pattern so as to form a corrected first sub-layout pattern and an OPC calculation based on a second OPC model is performed on the second sub-layout pattern so as to form a corrected second sub-layout pattern. Afterward, the corrected first sub-layout pattern and the corrected second sub-layout pattern are output from the computer system into a photomask.

Abstract translation: 光学邻近校正（OPC）的方法包括以下步骤。 首先，向计算机系统提供布局图案。 随后，将布局图案分为第一子布局图案和第二子布局图案。 然后，对第一子布局图案执行基于第一OPC模型的OPC计算，以形成校正的第一子布局图案，并且对第二子布局图案执行基于第二OPC模型的OPC计算 以形成校正的第二子布局图案。 之后，将校正的第一子布局图案和校正的第二子布局图案从计算机系统输出到光掩模中。

公开(公告)号：US09905562B2

公开(公告)日：2018-02-27

申请号：US15484126

申请日：2017-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry Che Jen Hu ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L27/118 ,  H01L27/092 ,  H01L27/02 ,  H01L29/06 ,  H01L27/088 ,  H01L23/522 ,  H01L23/528 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/785 ,  H01L2224/48132 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor IC layout structure includes a plurality of first active regions arranged along a second direction, a plurality of second active regions arranged along the second direction, a plurality of gate structures extending along a first direction and respectively straddling the first active regions and the second active regions, a plurality of first conductive structures extending along the first direction, and a plurality of second conductive structures formed on the gate structures. The second active regions are isolated from the first active regions. The first direction is perpendicular to the second direction. The first conductive structures are formed on the first active regions and the second active regions. The second conductive structures include a plurality of slot-type second conductive structures extended along the second direction and a plurality of island-type second conductive structures formed on the gate structures.

公开(公告)号：US09747404B2

公开(公告)日：2017-08-29

申请号：US14807869

申请日：2015-07-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Ming Kuo ,  Ming-Jui Chen ,  Te-Hsien Hsieh ,  Ping-I Hsieh ,  Jing-Yi Lee ,  Yan-Chun Chen

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5072 ,  G03F1/36 ,  G06F17/5081

Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.

公开(公告)号：US20170178716A1

公开(公告)日：2017-06-22

申请号：US15448599

申请日：2017-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Yu-Cheng Tung ,  Chin-Sheng Yang

IPC: G11C11/417 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104

Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

公开(公告)号：US09673145B2

公开(公告)日：2017-06-06

申请号：US14859367

申请日：2015-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry Che Jen Hu ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L29/82 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06 ,  H01L23/522 ,  H01L23/00 ,  H01L27/02 ,  H01L27/118

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/785 ,  H01L2224/48132 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor integrated circuit layout structure includes a first active region, a second active region isolating from the first active region, a gate structure straddling the first active region and the second active region, and a plurality of conductive structures. The first active region at two opposite sides of the gate structure respectively forms a first source region and a first drain region. The second active region at two opposite sides of the gate structure respectively forms a second source region and a second drain region. The conductive structures include a plurality of slot-type conductive structures and one island-type conductive structure. The slot-type conductive structures are respectively formed on the first source region, the first drain region, the second source region and the second drain region. The island-type conductive structure is formed on the gate structure.

公开(公告)号：US09613969B2

公开(公告)日：2017-04-04

申请号：US14793714

申请日：2015-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Wei-Cyuan Lo ,  Ming-Jui Chen ,  Chia-Lin Lu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Tan-Ya Yin ,  Chia-Wei Huang ,  Shu-Ru Wang ,  Yung-Feng Cheng

IPC: H01L27/11 ,  H01L29/76 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L21/823871 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/7851 ,  H01L29/7853

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

公开(公告)号：US20160351575A1

公开(公告)日：2016-12-01

申请号：US14793714

申请日：2015-07-07

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Wei-Cyuan Lo ,  Ming-Jui Chen ,  Chia-Lin Lu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Tan-Ya Yin ,  Chia-Wei Huang ,  Shu-Ru Wang ,  Yung-Feng Cheng

IPC: H01L27/11 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L21/823871 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/7851 ,  H01L29/7853

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

Abstract translation: 本发明提供一种半导体结构，其包括基板，多个翅片结构，多个栅极结构，电介质层和多个接触插塞。 衬底具有存储区域。 翅片结构设置在存储区域中的基板上，每个沿着第一方向延伸。 栅极结构设置在翅片结构上，每个翼结构沿着第二方向延伸。 电介质层设置在栅极结构和鳍结构上。 接触插头设置在电介质层中并电连接到鳍结构中的源极/漏极区域。 从顶部看，接触塞具有梯形或五边形。 本发明还提供了一种形成该方法的方法。

公开(公告)号：US20160329276A1

公开(公告)日：2016-11-10

申请号：US14859367

申请日：2015-09-21

Applicant: United Microelectronics Corp.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry CHE JEN HU ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L23/528 ,  H01L27/088 ,  H01L27/115 ,  H01L23/522 ,  H01L23/00 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/785 ,  H01L2224/48132 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor integrated circuit layout structure includes a first active region, a second active region isolating from the first active region, a gate structure straddling the first active region and the second active region, and a plurality of conductive structures. The first active region at two opposite sides of the gate structure respectively forms a first source region and a first drain region. The second active region at two opposite sides of the gate structure respectively forms a second source region and a second drain region. The conductive structures include a plurality of slot-type conductive structures and one island-type conductive structure. The slot-type conductive structures are respectively formed on the first source region, the first drain region, the second source region and the second drain region. The island-type conductive structure is formed on the gate structure.

Abstract translation: 半导体集成电路布局结构包括第一有源区，与第一有源区隔离的第二有源区，跨过第一有源区和第二有源区的栅极结构以及多个导电结构。 栅极结构的两个相对侧的第一有源区分别形成第一源极区域和第一漏极区域。 栅极结构的两个相对侧的第二有源区分别形成第二源极区和第二漏极区。 导电结构包括多个槽型导电结构和一个岛型导电结构。 槽型导电结构分别形成在第一源极区域，第一漏极区域，第二源极区域和第二漏极区域上。 岛型导电结构形成在栅极结构上。

公开(公告)号：US20160306910A1

公开(公告)日：2016-10-20

申请号：US14690491

申请日：2015-04-20

Applicant: United Microelectronics Corp.

Inventor： Ting-Cheng Tseng ,  Ming-Jui Chen ,  Chia-Wei Huang

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5081

Abstract: A method for decomposing a layout of an integrated circuit is provided. First, a layout of the integrated circuit is imported, wherein the layout comprises a plurality of sub patterns in a cell region, and a first direction and a second direction are defined thereon. Next, one sub pattern positioned at a corner of the cell region is assigned to an anchor pattern. Then, the sub patterns in the row same as the anchor pattern along the second direction is assigned to the first group. Finally, the rest of the sub patterns are decomposed into the first group and the second group according to a design rule, wherein the sub patterns in the same line are decomposed into the first group and the second group alternatively.

Abstract translation: 提供一种用于分解集成电路的布局的方法。 首先，导入集成电路的布局，其中布局包括单元区域中的多个子图案，并且在其上限定第一方向和第二方向。 接下来，将位于单元格区域的角落的一个子图案分配给锚图案。 然后，将与沿着第二方向的锚定图案相同的行中的子图案分配给第一组。 最后，根据设计规则，剩余的子图案被分解为第一组和第二组，其中同一行中的子图案被分解成第一组和第二组。

公开(公告)号：US09274416B2

公开(公告)日：2016-03-01

申请号：US14023476

申请日：2013-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Hsin-Yu Chen ,  Kai-Lin Chuang

IPC: G03F1/72 ,  G03F1/00

CPC classification number: G03F1/72 ,  G03F1/144 ,  G03F1/36

Abstract: A method for forming a photo-mask is provided. A first photo-mask pattern relating to a first line, an original second photo-mask pattern relating to a first via plug, and a third photo-mask pattern relating to a second line are provided. A first optical proximity correction (OPC) process is performed. A second OPC process is performed, comprising enlarging a width of the second photo-mask pattern along the first direction to form a revised second photo-resist pattern. A contour simulation process is performed to make sure the revised second photo-mask pattern is larger or equal to the original second-mask pattern. The first photo-mask pattern, the revised second photo-mask pattern, and the third photo-mask pattern are output. The present invention further provides an OPC method.

Abstract translation: 提供一种形成光掩模的方法。 提供与第一行相关的第一照片掩模图案，与第一通孔插头相关的原始第二照片掩模图案和与第二行相关的第三照片掩模图案。 执行第一光学邻近校正（OPC）处理。 执行第二OPC处理，包括沿着第一方向放大第二光掩模图案的宽度以形成修改的第二光刻胶图案。 执行轮廓模拟处理以确保修改的第二光掩模图案大于或等于原始第二掩模图案。 输出第一光掩模图案，修改的第二光掩模图案和第三光掩模图案。 本发明还提供一种OPC方法。