公开(公告)号：US09852952B2

公开(公告)日：2017-12-26

申请号：US14925955

申请日：2015-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chung Wang ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Nien-Chung Li ,  Shu-Wen Lin

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/49 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L21/82345 ,  H01L21/28035 ,  H01L21/31051 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV) region; forming a first gate structure on the logic region and a second gate structure on the HV region; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned hard mask on the HV region; and transforming the first gate structure into a metal gate.

公开(公告)号：US20170330948A1

公开(公告)日：2017-11-16

申请号：US15668708

申请日：2017-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Chih-Chung Wang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  G06F17/50

CPC classification number: H01L29/4238 ,  G06F17/5072 ,  H01L23/535 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/785

Abstract: A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug pattern in the gate pattern for producing a modified gate layout in a case where any one of a length and a width of the gate pattern is greater than or equal to a predetermined size, and outputting and manufacturing the modified gate layout onto a photomask. The predetermined size is determined by a process ability limit, and the process ability limit is a smallest gate size causing gate dishing when a chemical mechanical polishing process is performed to a gate.

公开(公告)号：US09741850B1

公开(公告)日：2017-08-22

申请号：US15235320

申请日：2016-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Ping-Hung Chiang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Kuan-Liang Liu ,  Kai-Kuen Chang

IPC: H01L29/745 ,  H01L29/76 ,  H01L23/58 ,  H01L21/00 ,  H01L21/336 ,  H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7835 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/1087 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7834

Abstract: A semiconductor device having a substrate, a gate electrode, a source and a drain, and a buried gate dielectric layer is disclosed. The buried gate dielectric layer is disposed below said gate electrode and protrudes therefrom to said drain, thereby separating said gate electrode and said drain by a substantial distance to reduce gate induced drain leakage.

公开(公告)号：US09691911B1

公开(公告)日：2017-06-27

申请号：US14995174

申请日：2016-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L27/06 ,  H01L29/872 ,  H01L29/06

CPC classification number: H01L29/8725 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/872

Abstract: A semiconductor device include a substrate, a first well region formed in the substrate, a first isolation structure formed in the first well region, a Schottky barrier structure formed on the first well region, and a plurality of assist structures formed on the first well region. The substrate includes a first conductivity type, the first well region includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The assist structures physically contact the first well region.

公开(公告)号：US20170179306A1

公开(公告)日：2017-06-22

申请号：US14995174

申请日：2016-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L29/872 ,  H01L29/06

CPC classification number: H01L29/8725 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/872

Abstract: A semiconductor device include a substrate, a first well region formed in the substrate, a first isolation structure formed in the first well region, a Schottky barrier structure formed on the first well region, and a plurality of assist structures formed on the first well region. The substrate includes a first conductivity type, the first well region includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The assist structures physically contact the first well region.

公开(公告)号：US09653343B1

公开(公告)日：2017-05-16

申请号：US15172136

申请日：2016-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuen Chang ,  Shih-Yin Hsiao ,  Chang-Po Hsiung

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L21/76235 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42364

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate having a first region and a second region is provided, a shallow trench isolation (STI) is formed in the substrate to separate the first region and the second region, and a patterned hard mask is formed on the first region and part of the STI, in which the patterned hard mask exposes includes an opening to expose part of the STI. Next, a gas is driven-in through the exposed STI to alter an edge of the substrate on the first region.

公开(公告)号：US20170125583A1

公开(公告)日：2017-05-04

申请号：US14930596

申请日：2015-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kun-Huang Yu

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1087 ,  H01L29/42364 ,  H01L29/7836

Abstract: A high voltage transistor includes a substrate, a well which is disposed within the substrate, a gate disposed on the well, a gate dielectric layer disposed between the well and the gate, two drift regions respectively disposed in the well at two sides of the gate, two source/drain regions respectively disposed within each drift region, wherein a width of the gate dielectric layer is smaller than a width of the source/drain region, and two isolation elements respectively disposed within each drift region

公开(公告)号：US20170125547A1

公开(公告)日：2017-05-04

申请号：US15406355

申请日：2017-01-13

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L29/66492 ,  H01L21/2652 ,  H01L21/31111 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method of forming a semiconductor device is provided. At least two shallow trenches are formed in a substrate. An insulating layer is formed on surfaces of the substrate and the shallow trenches. A conductive layer is formed on the substrate between the shallow trenches. At least one spacer is formed on a sidewall of the conductive layer, wherein the spacer fills up each shallow trench.

公开(公告)号：US20170062279A1

公开(公告)日：2017-03-02

申请号：US14835700

申请日：2015-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sih-Yun Wei ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L21/8238 ,  H01L21/266 ,  H01L27/092 ,  H01L29/66 ,  H01L21/265 ,  H01L29/167

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/6659

Abstract: A transistor set forming process includes the following steps. A substrate having a first area and a second area is provided. An implantation process is performed to form a diffusion region of a first transistor in the substrate of the first area and a channel region of a second transistor in the substrate of the second area at the same time.

Abstract translation: 晶体管组形成工艺包括以下步骤。 提供具有第一区域和第二区域的衬底。 执行注入工艺，以在第一区域的衬底中的第一晶体管的扩散区域和第二区域的衬底中的第二晶体管的沟道区域同时形成。

公开(公告)号：US09583617B2

公开(公告)日：2017-02-28

申请号：US14737186

申请日：2015-06-11

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/70 ,  H01L29/78

CPC classification number: H01L29/66492 ,  H01L21/2652 ,  H01L21/31111 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833

Abstract: Provided is a semiconductor device including a substrate, an insulating layer, a conductive layer and at least one spacer. The substrate has at least two shallow trenches therein. The conductive layer is disposed on the substrate between the shallow trenches. The insulating layer is disposed between the substrate and the conductive layer. The at least one spacer is disposed on one sidewall of the conductive layer and fills up each shallow trench. A method of forming a semiconductor device is further provided.

Abstract translation: 提供了一种半导体器件，其包括衬底，绝缘层，导电层和至少一个间隔物。 衬底中具有至少两个浅沟槽。 导电层设置在浅沟槽之间的衬底上。 绝缘层设置在基板和导电层之间。 至少一个间隔件设置在导电层的一个侧壁上并填充每个浅沟槽。 还提供了形成半导体器件的方法。