公开(公告)号：US08153514B2

公开(公告)日：2012-04-10

申请号：US12187767

申请日：2008-08-07

申请人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, Jr. ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, Jr. ,  Sufi Zafar

IPC分类号： H01L21/3205

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高迁移率和低界面电荷的栅叠层结构，以及包括其的半导体器件即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。 本发明中使用的高温退火提供了一种栅极叠层结构，其具有约8×10 10电荷/ cm 2或更小的峰值迁移率，约250cm 2 / s或更大的峰迁移率的通过电荷泵浦测量的界面状态密度，以及 在大约6.0×10 12反转电荷/ cm 2或更大时基本上没有迁移率降解。

公开(公告)号：US20100044805A1

公开(公告)日：2010-02-25

申请号：US12609555

申请日：2009-10-30

申请人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L29/78

CPC分类号： H01L21/28088 ,  H01L21/28518 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

摘要： A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.

摘要翻译： 提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。 本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含金属层的底部至顶部。 通过利用具有小于1.1的金属与氮的组成比的金属含氮层来实现提高的可靠性。 本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。 本发明还提供一种制造这种栅叠层的方法，其中改变溅射工艺的工艺条件以控制溅射沉积层内的金属和氮的比例。

公开(公告)号：US07611979B2

公开(公告)日：2009-11-03

申请号：US11673901

申请日：2007-02-12

申请人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L21/3205 ,  H01L21/28

CPC分类号： H01L21/28088 ,  H01L21/28518 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

摘要： A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.

摘要翻译： 提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。 本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含金属层的底部至顶部。 通过利用具有小于1.1的金属与氮的组成比的金属含氮层来实现提高的可靠性。 本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。 本发明还提供一种制造这种栅叠层的方法，其中改变溅射工艺的工艺条件以控制溅射沉积层内的金属和氮的比例。

公开(公告)号：US09059314B2

公开(公告)日：2015-06-16

申请号：US13602118

申请日：2012-09-01

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

摘要翻译： 提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。 在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠 材料掺杂元素。 在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。 在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

公开(公告)号：US08304836B2

公开(公告)日：2012-11-06

申请号：US12620234

申请日：2009-11-17

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC分类号： H01L21/70

CPC分类号： H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

摘要翻译： 提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。 在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠 材料掺杂元素。 在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。 在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

公开(公告)号：US20110115027A1

公开(公告)日：2011-05-19

申请号：US12620234

申请日：2009-11-17

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/263

CPC分类号： H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

摘要翻译： 提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。 在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠 材料掺杂元素。 在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。 在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

公开(公告)号：US20080299730A1

公开(公告)日：2008-12-04

申请号：US12190129

申请日：2008-08-12

申请人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L21/336 ,  C23C14/34

CPC分类号： H01L21/28088 ,  H01L21/823828 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MOxNy compound metal. Furthermore, the MOxNy metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (pMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.

摘要翻译： 包含MoxNy的复合金属是具有在包括高k电介质和界面层的栅叠层上热稳定的功函数为约4.75至约5.3，优选约5e的功函数的p型金属，以及 制造MOxNy复合金属的方法。 此外，本发明的MOxNy金属化合物在1000℃下是非常有效的氧扩散阻挡层，允许在p金属氧化物半导体（pMOS）器件中非常有侵蚀性的等效氧化物厚度（EOT）和低于14的反型层厚度标度 。 在上式中，M是选自元素周期表第IVB，VB，VIB或VIIB族的金属，x为约5至约40原子％，y为约5至约40原子％。

公开(公告)号：US07436034B2

公开(公告)日：2008-10-14

申请号：US11311455

申请日：2005-12-19

申请人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L21/00

CPC分类号： H01L21/28088 ,  H01L21/823828 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MOxNy compound metal. Furthermore, the MOxNy metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (PMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.

摘要翻译： 一种复合金属，其包含具有约4.75至约5.3，优选约5eV的功函数的p型金属，其在一个或多个金属上是热稳定的 提供了包括高k电介质和界面层的栅极叠层以及制造复合金属的方法。 此外，本发明的金属氧化物金属化合物在1000℃下是非常有效的氧扩散阻挡层，允许非常有效的等效氧化物厚度（EOT）和反演 在p-金属氧化物半导体（PMOS）器件中的层厚度缩小到14埃以下。 在上式中，M是选自元素周期表第IVB，VB，VIB或VIIB族的金属，x为约5至约40原子％，y为约5至约40原子％。

公开(公告)号：US07115959B2

公开(公告)日：2006-10-03

申请号：US10873733

申请日：2004-06-22

申请人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evengi Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph P. Shepard, Jr. ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evengi Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph P. Shepard, Jr. ,  Sufi Zafar

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

公开(公告)号：US07776701B2

公开(公告)日：2010-08-17

申请号：US12190129

申请日：2008-08-12

申请人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/469 ,  H01L21/31 ,  H01L21/8234

CPC分类号： H01L21/28088 ,  H01L21/823828 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MOxNy compound metal. Furthermore, the MOxNy metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (pMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.

摘要翻译： 包含MoxNy的复合金属是具有在包括高k电介质和界面层的栅叠层上热稳定的功函数为约4.75至约5.3，优选约5e的功函数的p型金属，以及 制造MOxNy复合金属的方法。 此外，本发明的MOxNy金属化合物在1000℃下是非常有效的氧扩散阻挡层，允许在p金属氧化物半导体（pMOS）器件中非常有侵蚀性的等效氧化物厚度（EOT）和低于14的反型层厚度标度 。 在上式中，M是选自元素周期表第IVB，VB，VIB或VIIB族的金属，x为约5至约40原子％，y为约5至约40原子％。