公开(公告)号：US08053848B2

公开(公告)日：2011-11-08

申请号：US12381380

申请日：2009-03-11

申请人： Jin-Sung Lee ,  Woon-Kyung Lee

发明人： Jin-Sung Lee ,  Woon-Kyung Lee

IPC分类号： H01L29/66

CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573

摘要： A semiconductor device includes a plurality of transistors disposed on a semiconductor substrate, a device isolation layer disposed around the transistors, a guard ring disposed to surround the device isolation layer and the transistors, and a guard region disposed between adjacent transistors.

摘要翻译： 半导体器件包括设置在半导体衬底上的多个晶体管，围绕晶体管设置的器件隔离层，设置成围绕器件隔离层和晶体管的保护环以及设置在相邻晶体管之间的保护区。

公开(公告)号：US08036043B2

公开(公告)日：2011-10-11

申请号：US12480352

申请日：2009-06-08

申请人： Dong-Yean Oh ,  Woon-Kyung Lee

发明人： Dong-Yean Oh ,  Woon-Kyung Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/3454 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11551 ,  H01L27/11556

摘要： A nonvolatile semiconductor memory device including a vertical array structure comprised of bit lines and source lines arranged in the same direction as the bit lines, each source lines corresponding to the bit lines and memory cell strings vertically formed between each pair of the bit lines and source lines. Multiple strings of memory cells can be stacked in the vertical direction, and adjacent memory cell strings may share bit line or source line.

摘要翻译： 一种非易失性半导体存储器件，包括垂直阵列结构，其包括与位线相同方向布置的位线和源极线，每个源极线对应于在每对位线和源极之间垂直形成的位线和存储单元串 线条。 多个存储单元串可以在垂直方向堆叠，并且相邻的存储单元串可以共享位线或源极线。

公开(公告)号：US08035149B2

公开(公告)日：2011-10-11

申请号：US12913865

申请日：2010-10-28

申请人： Woon-Kyung Lee

发明人： Woon-Kyung Lee

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A nonvolatile memory device includes an active region defined by a device isolation layer in a semiconductor substrate, a word line passing over the active region and a charge storage region defined by a crossing of the active region and the word line and disposed between the active region and the word line. The charge storage region is disposed at an oblique angle with respect to the word line.

摘要翻译： 非易失性存储器件包括由半导体衬底中的器件隔离层限定的有源区，通过有源区的字线和由有源区和字线的交叉限定的电荷存储区，并且设置在有源区 和字线。 电荷存储区域相对于字线倾斜设置。

公开(公告)号：US20110220985A1

公开(公告)日：2011-09-15

申请号：US13044766

申请日：2011-03-10

申请人： Jung-Min Son ,  Woon-Kyung Lee

发明人： Jung-Min Son ,  Woon-Kyung Lee

IPC分类号： H01L27/06 ,  H01L29/423 ,  H01L29/788 ,  H01L21/28

CPC分类号： H01L29/788 ,  H01L27/11521

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件可以包括电荷存储结构和栅极。 电荷存储结构形成在基板上。 栅极形成在电荷存储结构上。 栅极包括由硅形成的下部和由金属硅化物形成的上部。 栅极的上部具有大于栅极下部的宽度的宽度。

公开(公告)号：US20090296477A1

公开(公告)日：2009-12-03

申请号：US12437209

申请日：2009-05-07

申请人： Jong-Won Kim ,  Woon-Kyung Lee

发明人： Jong-Won Kim ,  Woon-Kyung Lee

IPC分类号： G11C16/04 ,  H01L29/788 ,  H01L29/792 ,  G11C7/02

CPC分类号： H01L27/11568 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate including a cell array region, memory cell transistors disposed at the cell array region, bitlines disposed on the memory cell transistors, and a source plate disposed between the memory cell transistors and the bitlines to veil the memory cell transistors thereunder.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括：半导体衬底，包括单元阵列区域，设置在单元阵列区域的存储单元晶体管，设置在存储单元晶体管上的位线;以及设置在存储单元晶体管和位线之间的源极，以对存储单元晶体管 在那里

公开(公告)号：US06573574B2

公开(公告)日：2003-06-03

申请号：US10178626

申请日：2002-06-24

申请人： Woon-Kyung Lee

发明人： Woon-Kyung Lee

IPC分类号： H01L2976

CPC分类号： H01L27/11266 ,  G11C17/126 ,  H01L27/112 ,  Y10S257/908

摘要： In a cell array region of a NOR-type mask ROM device and a fabricating method therefor, following formation of a plurality of word lines parallel to one another on a semiconductor substrate, a plurality of sub-bit lines intersecting the top portion of the plurality of word lines at right angles are formed. Trench regions are formed on the semiconductor substrate exposed by the plurality of word lines and the plurality of sub-bit lines. An interlayer insulating layer is formed on the entire surface of the resulting material, and a plurality of bit lines which are parallel to one another are formed on the interlayer insulating layer.

公开(公告)号：US06555865B2

公开(公告)日：2003-04-29

申请号：US09902820

申请日：2001-07-10

申请人： Joon-Sung Lee ,  Woon-Kyung Lee

发明人： Joon-Sung Lee ,  Woon-Kyung Lee

IPC分类号： H01L2976

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/792

摘要： The present invention provides a nonvolatile memory device having high reliability with novel sidewall spacer structures. The gate stack structure for use in a nonvolatile memory device comprises a semiconductor substrate, a gate stack formed on the semiconductor substrate. The gate stack has a sidewall and a top surface. A multi-layer sidewall spacer structure is formed on the sidewall of the gate stack. The multi-layer sidewall spacer structure includes a first oxide layer, a first nitride layer, a second oxide layer, and a second nitride layer that are sequentially stacked. With the present invention, even if the second nitride layer is perforated or damaged during the formation of contact holes, sidewalls of the gate stack of nonvolatile memory cell can be protected with the first nitride layer from mobile ions. Also, etching damage to source/drain regions or field regions can be reduced.

摘要翻译： 本发明提供一种具有高可靠性的新型侧壁间隔结构的非易失性存储器件。 用于非易失性存储器件的栅极堆叠结构包括半导体衬底，形成在半导体衬底上的栅叠层。 栅极堆叠具有侧壁和顶部表面。 在栅叠层的侧壁上形成多层侧壁间隔结构。 多层侧壁间隔结构包括依次堆叠的第一氧化物层，第一氮化物层，第二氧化物层和第二氮化物层。 利用本发明，即使在形成接触孔期间第二氮化物层被穿孔或损坏，非易失性存储单元的栅极堆叠的侧壁可以被移动离子的第一氮化物层保护。 此外，可以减少对源极/漏极区域或场区域的蚀刻损伤。

公开(公告)号：US5923606A

公开(公告)日：1999-07-13

申请号：US954905

申请日：1997-10-21

申请人： Woon-Kyung Lee ,  Eui-Do Kim

发明人： Woon-Kyung Lee ,  Eui-Do Kim

IPC分类号： H01L21/8246 ,  H01L27/112 ,  G11C13/00

CPC分类号： H01L27/112

摘要： A NOR-type mask ROM reduces the resistance ratio of buried diffusion layers and improves the drive capacity of bank selection transistors by utilizing sub-bit line selection transistors located near the center of a memory cell array. The sub-bit line selection transistors are connected to a pair of sub-bank selection lines that divide the memory cell array into symmetric upper and lower portions. The bank selection transistors couple alternate sub-bit lines to main bit lines at both ends of the sub-bit lines, thereby forming a dual current path between the main bit lines and the memory cells coupled to the sub-bit lines.

摘要翻译： NOR型掩模ROM通过利用位于存储单元阵列中心附近的子位线选择晶体管来降低掩埋扩散层的电阻比，并且提高了存储体选择晶体管的驱动能力。 子位线选择晶体管连接到将存储单元阵列分成对称的上部和下部的一对子组选择线。 存储体选择晶体管将副位线耦合到子位线两端的主位线，从而在主位线和耦合到子位线的存储单元之间形成双电流路径。

公开(公告)号：US09209244B2

公开(公告)日：2015-12-08

申请号：US13717803

申请日：2012-12-18

申请人： Jae-Joo Shim ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Ju-Young Lim ,  Sung-Min Hwang

发明人： Jae-Joo Shim ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Ju-Young Lim ,  Sung-Min Hwang

IPC分类号： H01L29/06 ,  H01L27/02 ,  H01L27/115

CPC分类号： H01L29/0657 ,  H01L27/0207 ,  H01L27/1157 ,  H01L27/11582

摘要： Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.

摘要翻译： 提供了包括设置在基板上的第一和第二隔离图案的半导体器件。 交替层叠的层间绝缘图案和导电图案设置在第一和第二隔离图案之间的基板的表面上。 支撑图案穿透导电图案和层间绝缘图案，并且具有比第一和第二隔离图案更小的宽度。 第一和第二垂直结构设置在第一隔离和支撑图案之间并且穿透导电图案和层间绝缘图案。 第二垂直结构设置在第二隔离图案和支撑图案之间并且穿透导电图案和层间绝缘图案。 支撑图案的顶表面和底表面之间的距离大于支撑图案的底表面和基底表面之间的距离。

公开(公告)号：US08264025B2

公开(公告)日：2012-09-11

申请号：US12275369

申请日：2008-11-21

申请人： Seung-Jun Lee ,  Woon-Kyung Lee

发明人： Seung-Jun Lee ,  Woon-Kyung Lee

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile memory device and a method of forming a nonvolatile memory device are provided. The nonvolatile memory device includes an active region of a semiconductor substrate defined by a device isolation layer, a tunnel insulating structure disposed on the active region, and a charge storage structure disposed on the tunnel insulating structure. The nonvolatile memory device also includes a gate interlayer dielectric layer disposed on the charge storage structure, and a control gate electrode disposed on the gate interlayer dielectric layer. The charge storage structure includes an upper charge storage structure and a lower charge storage structure, and the upper charge storage structure has a higher impurity concentration than the lower charge storage structure.

摘要翻译： 提供了非易失性存储器件和形成非易失性存储器件的方法。 非易失性存储器件包括由器件隔离层限定的半导体衬底的有源区，设置在有源区上的隧道绝缘结构，以及设置在隧道绝缘结构上的电荷存储结构。 非易失性存储器件还包括设置在电荷存储结构上的栅极层间介质层和设置在栅极层间介质层上的控制栅电极。 电荷存储结构包括上电荷存储结构和较低电荷存储结构，并且上电荷存储结构具有比下电荷存储结构更高的杂质浓度。