公开(公告)号：US11195780B1

公开(公告)日：2021-12-07

申请号：US16828822

申请日：2020-03-24

Applicant: XILINX, INC.

Inventor： Jaspreet Singh Gandhi ,  Gamal Refai-Ahmed ,  Suresh Ramalingam

IPC: H01L31/12 ,  H01L23/427 ,  H01L23/373 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/10

Abstract: A chip package assembly and method for fabricating the same are provided which incorporate phase change materials within the chip package assembly for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die stacked on the substrate, a dielectric filler layer, a cover and a phase change material. The phase change material is sealed within a recess formed between the first IC dies and the cover.

公开(公告)号：US11145566B2

公开(公告)日：2021-10-12

申请号：US16786447

申请日：2020-02-10

Applicant: XILINX, INC.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Cheang-Whang Chang

IPC: H01L23/367 ,  H01L25/065

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating heat transfer structures for improved thermal management. In one example, a chip package assembly is provided. The chip package assembly includes a substrate, a first integrated circuit (IC) die and a plurality of electrically floating conductive heat transfer structures. The substrate has a first surface and an opposing second surface. The first IC die has a first surface, an opposing second surface, and four lateral sides. The second surface of the first IC die is mounted to the first surface of the substrate. The plurality of electrically floating conductive heat transfer structures extend in a first direction defined between the first and second surfaces of the first IC die. A first conductive heat transfer structure of the plurality of electrically floating conductive heat transfer structures are part of a first conductive heat transfer path having a length in the first direction at least as long as a distance between the first and second surfaces.

公开(公告)号：US10770364B2

公开(公告)日：2020-09-08

申请号：US15951941

申请日：2018-04-12

Applicant: Xilinx, Inc.

Inventor： Hong Shi ,  Suresh Ramalingam ,  Siow Chek Tan ,  Gamal Refai-Ahmed

IPC: H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065

Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die.

公开(公告)号：US20200152546A1

公开(公告)日：2020-05-14

申请号：US16186178

申请日：2018-11-09

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Ho Hyung Lee ,  Hui-Wen Lin ,  Henley Liu ,  Suresh Ramalingam

IPC: H01L23/40 ,  H01L23/48 ,  H01L23/00 ,  H01L23/427

Abstract: Examples described herein provide for an electronic device apparatus with multiple thermally conductive paths for heat dissipation. In an example, an electronic device apparatus includes a package comprising a die attached to a package substrate. The electronic device apparatus further includes a ring stiffener disposed around the die and on the package substrate, a heat sink disposed on the package, and a wedge disposed between the heat sink and the ring stiffener.

公开(公告)号：US10529645B2

公开(公告)日：2020-01-07

申请号：US15617774

申请日：2017-06-08

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Henley Liu ,  Tien-Yu Lee ,  Gamal Refai-Ahmed ,  Myongseob Kim ,  Ferdinand F. Fernandez ,  Ivor G. Barber ,  Suresh Ramalingam

IPC: H01L23/367 ,  H01L23/10 ,  H01L23/055 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.

公开(公告)号：US10527670B2

公开(公告)日：2020-01-07

申请号：US15471390

申请日：2017-03-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Ivor G. Barber ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Tien-Yu Lee ,  Henley Liu ,  David M. Mahoney ,  Mohsen H. Mardi

IPC: G01R31/28

Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.

公开(公告)号：US11355412B2

公开(公告)日：2022-06-07

申请号：US16147286

申请日：2018-09-28

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Gamal Refai-Ahmed ,  Henley Liu ,  Myongseob Kim ,  Tien-Yu Lee ,  Suresh Ramalingam ,  Cheang-Whang Chang

IPC: H01L23/367 ,  H01L23/427 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065 ,  H01L25/07

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.

公开(公告)号：US11330738B1

公开(公告)日：2022-05-10

申请号：US17133525

申请日：2020-12-23

Applicant: XILINX, INC.

Inventor： Gamal Refai-Ahmed ,  Chi-Yi Chao ,  Huayan Wang ,  Suresh Ramalingam ,  Volker Aue

IPC: H05K7/20 ,  H05K1/02 ,  H01Q1/00

Abstract: An electronic device is provided that balances the force applied to temperature control elements such that stress within components of the electronic device can be effectively managed. In one example, an electronic device is provided that includes a printed circuit board (PCB), a chip package, a thermal management system, a thermal spreader, and first and second biasing members. The chip package is mounted to the PCB. The thermal management system and spreader are disposed the opposite of the chip package relative to the PCB. The first biasing member is configured to control a first force sandwiching the chip package between the thermal spreader and the PCB. The second biasing member is configured to control a second force applied by the thermal management system against the thermal spreader. The first force can be adjusted separately from the second force so that total forces applied to the chip package and PCB may be effectively balanced.

公开(公告)号：US20200006186A1

公开(公告)日：2020-01-02

申请号：US16024670

申请日：2018-06-29

Applicant: Xilinx, Inc.

Inventor： Hong-Tsz Pan ,  Jonathan Chang ,  Nui Chong ,  Henley Liu ,  Gamal Refai-Ahmed ,  Suresh Ramalingam

IPC: H01L23/367 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/528

Abstract: A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface.

公开(公告)号：US20190318975A1

公开(公告)日：2019-10-17

申请号：US15951941

申请日：2018-04-12

Applicant: Xilinx, Inc.

Inventor： Hong Shi ,  Suresh Ramalingam ,  Siow Chek Tan ,  Gamal Refai-Ahmed

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367

Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die.