公开(公告)号：US11163605B1

公开(公告)日：2021-11-02

申请号：US16571776

申请日：2019-09-16

Applicant: XILINX, INC.

Inventor： Sonal Santan ,  Min Ma ,  Soren Soe ,  Cheng Zhen ,  Lizhi Hou ,  Yu Liu

IPC: G06F9/46 ,  G06F9/48

Abstract: Examples herein describe techniques for launching and executing a pipeline formed by heterogeneous processing units. A system on a chip (SoC) can include different hardware elements which form a collection of heterogeneous processing units, such as general purpose processor, programmable logic array, and specialized processors. These processing units are heterogeneous meaning their underlying hardware and techniques for processing data are different, in contrast to a system that using homogeneous processing units. In the embodiments herein, the heterogeneous processing units can be arranged into a pipeline where each stage of the pipeline is performed by one of the processing units.

公开(公告)号：US11042610B1

公开(公告)日：2021-06-22

申请号：US15724942

申请日：2017-10-04

Applicant: Xilinx, Inc.

Inventor： Hem C. Neema ,  Sonal Santan ,  Bin Ochotta

IPC: G06F21/00 ,  G06F21/12 ,  H04L9/32 ,  G06F21/77 ,  H04L29/06 ,  H04W12/06 ,  H04W12/10

Abstract: Embodiments herein describe techniques for validating binary files used to configure a hardware card in a computing system. In one embodiment, the hardware card (e.g., an FPGA) includes programmable logic which the binary file can configure to perform a specialized function. In one embodiment, multiple users can configure the hardware card to perform their specialized tasks. For example, the computing system may be server on the cloud that hosts multiple VMs or a shared workstation. Permitting multiple users to directly configure and use the hardware card may present a security risk. To mitigate this risk, the embodiments herein describe techniques for validating encrypted binary files.

公开(公告)号：US10819680B1

公开(公告)日：2020-10-27

申请号：US15915981

申请日：2018-03-08

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Umang Parekh ,  Jeffrey H. Seltzer ,  Khang K. Dao ,  Kyle Corbett

IPC: H04L29/06 ,  G06F13/42

Abstract: System and method generally relate to protection of a bussed network. In such a system, an access controller is configured for bussed communication via a communication bus to obtain a current transaction. An interface firewall is coupled for bussed communication with the access controller and configured to check for a fault associated with a transfer. A data processing device is coupled for communication with the interface firewall and configured to execute the current transaction to provide the transfer for the interface firewall. The interface firewall is configured to detect the fault associated with the transfer, to block access to the data processing device associated with the fault, and to communicate a blocked status for the data processing device.

公开(公告)号：US12204940B2

公开(公告)日：2025-01-21

申请号：US17648172

申请日：2022-01-17

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Yu Liu ,  Yenpang Lin ,  Stephen P. Rozum

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/54 ,  G06F12/02

Abstract: Remote kernel execution in a heterogeneous computing system can include executing, using a device processor of a device communicatively linked to a host processor, a device runtime and receiving from the host processor within a hardware submission queue of the device, a command. The command requests execution of a software kernel and specifies a descriptor stored in a region of a memory of the device shared with the host processor. In response to receiving the command, the device runtime, as executed by the device processor, invokes a runner program associated with the software kernel. The runner program can map a physical address of the descriptor to a virtual memory address corresponding to the descriptor that is usable by the software kernel. The runner program can execute the software kernel. The software kernel can access data specified by the descriptor using the virtual memory address as provided by the runner program.

公开(公告)号：US20240211302A1

公开(公告)日：2024-06-27

申请号：US18145662

申请日：2022-12-22

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Yu Liu ,  Akila Subramaniam ,  Vinod K. Kathail ,  King Chiu Tam ,  Tung Chuen Kwong ,  Pranjal Joshi ,  Soren T. Soe

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4843 ,  G06F9/5005 ,  G06F9/5061

Abstract: Dynamic provisioning of portions of a data processing array includes receiving, from an executing application, a context request. The context request specifies a requested task to be performed by a data processing array. A configuration for the data processing array is selected from a plurality of configurations for the data processing array. The selected configuration conforms with the context request and is capable of performing the requested task. A determination is made whether the selected configuration is implementable in the data processing array based, at least in part, on a space requirement of the selected configuration and a current status of the data processing array. The selected configuration is selectively implemented in the data processing array based on the determination.

公开(公告)号：US11947469B2

公开(公告)日：2024-04-02

申请号：US17675897

申请日：2022-02-18

Applicant: XILINX, INC.

Inventor： Cheng Zhen ,  Sonal Santan ,  Min Ma ,  Chien-Wei Lan

IPC: G06F13/10 ,  G06F13/42

CPC classification number: G06F13/102 ,  G06F13/4221 ,  G06F2213/0026

Abstract: Embodiments herein describe partitioning an acceleration device based on the needs of each user application executing in a host. In one embodiment, a flexible queue provisioning method allows the acceleration device to be dynamically partitioned by pushing the configuration through a control command queue to the device by management software running in a trusted zone. The new configuration is parsed and verified by trusted firmware, which, then, creates isolated IO command queues on the acceleration device. These IO command queues can be directly mapped to a user application, VM, or other PCIe devices. In one embodiment, each IO command queue exposes only the compute resource assigned by the trusted firmware in the acceleration device.

公开(公告)号：US11694066B2

公开(公告)日：2023-07-04

申请号：US15785679

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Aaron Ng ,  Jindrich Zejda ,  Elliott Delaye ,  Xiao Teng ,  Sonal Santan ,  Soren T. Soe ,  Ashish Sirasao ,  Ehsan Ghasemi ,  Sean Settle

IPC: G06N3/063 ,  G06N3/10 ,  G06N3/08 ,  G06N3/04 ,  G06V10/94 ,  G06N3/045

CPC classification number: G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G06N3/10 ,  G06N3/045 ,  G06V10/955

Abstract: Embodiments herein describe techniques for interfacing a neural network application with a neural network accelerator using a library. The neural network application may execute on a host computing system while the neural network accelerator executes on a massively parallel hardware system, e.g., a FPGA. The library operates a pipeline for submitting the tasks received from the neural network application to the neural network accelerator. In one embodiment, the pipeline includes a pre-processing stage, an FPGA execution stage, and a post-processing stage which each correspond to different threads. When receiving a task from the neural network application, the library generates a packet that includes the information required for the different stages in the pipeline to perform the tasks. Because the stages correspond to different threads, the library can process multiple packets in parallel which can increase the utilization of the neural network accelerator on the hardware system.

公开(公告)号：US11386034B2

公开(公告)日：2022-07-12

申请号：US17085740

申请日：2020-10-30

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Ravi N. Kurlagunda ,  Min Ma ,  Himanshu Choudhary ,  Manjunath Chepuri ,  Cheng Zhen ,  Pranjal Joshi ,  Sebastian Turullols ,  Amit Kumar ,  Kaustuv Manji ,  Ravinder Sharma ,  Ch Vamshi Krishna

IPC: G06F13/42

Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

公开(公告)号：US20220138140A1

公开(公告)日：2022-05-05

申请号：US17085740

申请日：2020-10-30

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Ravi N. Kurlagunda ,  Min Ma ,  Himanshu Choudhary ,  Manjunath Chepuri ,  Cheng Zhen ,  Pranjal Joshi ,  Sebastian Turullols ,  Amit Kumar ,  Kaustuv Manji ,  Ravinder Sharma ,  Ch Vamshi Krishna

IPC: G06F13/42

Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

公开(公告)号：US10802995B2

公开(公告)日：2020-10-13

申请号：US16046602

申请日：2018-07-26

Applicant: Xilinx, Inc.

Inventor： Sarabjeet Singh ,  Hem C. Neema ,  Sonal Santan ,  Khang K. Dao ,  Kyle Corbett ,  Yi Wang ,  Christopher J. Case

IPC: G06F9/38 ,  G06F13/16 ,  G06F9/46 ,  G06F12/0873 ,  G06F12/1045 ,  G06F12/1081

Abstract: A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.