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114 条记录 (耗时 0.027 秒)

    Stacked and tunable power fuse
    21.
    发明授权
    Stacked and tunable power fuse 有权
    堆叠和可调电源保险丝

    公开(公告)号：US08598679B2

    公开(公告)日：2013-12-03

    申请号：US12956025

    申请日：2010-11-30

    申请人： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

    发明人： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

    IPC分类号： H01L23/52

    CPC分类号： H01L27/0288 ,  H01L23/5256 ,  H01L27/0255 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.

    摘要翻译： 本公开提供了一种半导体器件，其包括晶体管，其包括衬底，源极，漏极和栅极以及堆叠在晶体管上的熔丝。 保险丝包括耦合到晶体管的漏极的阳极触点，阴极触点和分别经由第一肖特基二极管和第二肖特基二极管耦合到阴极触点和阳极触点的电阻器。 还提供了一种制造这种半导体器件的方法。

    High voltage transistor structure for semiconductor device
    24.
    发明授权
    High voltage transistor structure for semiconductor device 有权
    半导体器件用高压晶体管结构

    公开(公告)号：US07525155B2

    公开(公告)日：2009-04-28

    申请号：US11387573

    申请日：2006-03-23

    申请人： Fu-Hsin Chen ,  Ruey-Hsin Liu

    发明人： Fu-Hsin Chen ,  Ruey-Hsin Liu

    IPC分类号： H01L29/94 ,  H01L29/74

    CPC分类号： H01L29/66659 ,  H01L29/0692 ,  H01L29/7835

    摘要： A high voltage MOS transistor has a thermally-driven-in first doped region and a second doped region that form a double diffused drain structure. Boundaries of the first doped region are graded. A gate-side boundary of the first doped region extends laterally below part of the gate electrode. The second doped region is formed within the first doped region. A gate-side boundary of the second doped region is separated from a closest edge of the gate electrode by a first spaced distance. The gate-side boundary of the second doped region is separated from a closest edge of the spacer by a second spaced distance. The first spaced distance is greater than the second spaced distance. An isolation-side boundary of the second doped region may be separated from an adjacent isolation structure by a third spaced distance.

    摘要翻译： 高压MOS晶体管具有热驱动的第一掺杂区域和形成双扩散漏极结构的第二掺杂区域。 第一掺杂区域的边界被分级。 第一掺杂区的栅极侧边界在栅电极的一部分的横向下方延伸。 第二掺杂区域形成在第一掺杂区域内。 第二掺杂区域的栅极侧边界与栅电极的最近边缘隔开第一间隔距离。 第二掺杂区域的栅极侧边界与间隔物的最近边缘隔开第二间隔距离。 第一间隔距离大于第二间隔距离。 第二掺杂区域的隔离侧边界可以与相邻隔离结构隔开第三间隔距离。

    Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
    27.
    发明授权
    Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology 失效
    为BiCMOS / CMOS技术形成浅沟槽深沟槽隔离区域的方法

    公开(公告)号：US07015086B2

    公开(公告)日：2006-03-21

    申请号：US10772940

    申请日：2004-02-05

    申请人： Kuan-Lun Chang ,  Ruey-Hsin Liu ,  Tsyr-Shyang Liou ,  Chih-Min Chiang ,  Jun-Lin Tsai

    发明人： Kuan-Lun Chang ,  Ruey-Hsin Liu ,  Tsyr-Shyang Liou ,  Chih-Min Chiang ,  Jun-Lin Tsai

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76232 ,  H01L21/763

    摘要： A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized via a first chemical mechanical polishing procedure, allowing reduced complexity to be realized during the subsequent formation of a narrow diameter, deep trench opening, in the insulator filled shallow trench shape and in an underlying portion of semiconductor substrate. Formation of a recessed polysilicon plug located in the bottom portion of the deep trench opening is followed by formation of an insulator plug located in a top portion of the deep trench opening, overlying the recessed polysilicon plug. This is accomplished via photolithographic and selective dry definition procedures, and a second chemical mechanical polishing procedure, resulting in a filled, deep trench opening exhibiting a smooth top surface topography.

    摘要翻译： 已经开发了用于形成由浅沟槽 - 深沟槽构造构成的隔离区域的工艺，其中获得用于隔离区域和半导体衬底中的相邻有源器件区域的平滑顶表面形貌。 该工艺特征最初形成通过第一化学机械抛光工艺平坦化的绝缘体填充的浅沟槽形状，允许在随后形成在绝缘体填充的浅沟槽形状中的窄直径，深沟槽开口期间实现降低的复杂性 半导体衬底的下面部分。 位于深沟槽开口底部的凹陷多晶硅插塞的形成之后，形成位于深沟槽开口的顶部的绝缘体塞，覆盖凹入的多晶硅插塞。 这通过光刻和选择性干法定义程序和第二化学机械抛光程序来实现，从而产生填充的深沟槽开口，表现出光滑的顶表面形貌。

    Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
    28.
    发明申请
    Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology 失效
    为BiCMOS / CMOS技术形成浅沟槽深沟槽隔离区域的方法

    公开(公告)号：US20050176214A1

    公开(公告)日：2005-08-11

    申请号：US10772940

    申请日：2004-02-05

    申请人： Kuan-Lun Chang ,  Ruey-Hsin Liu ,  Tsyr-Shyang Liou ,  Chih-Min Chiang ,  Jun-Lin Tsai

    发明人： Kuan-Lun Chang ,  Ruey-Hsin Liu ,  Tsyr-Shyang Liou ,  Chih-Min Chiang ,  Jun-Lin Tsai

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763

    CPC分类号： H01L21/76232 ,  H01L21/763

    摘要： A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized via a first chemical mechanical polishing procedure, allowing reduced complexity to be realized during the subsequent formation of a narrow diameter, deep trench opening, in the insulator filled shallow trench shape and in an underlying portion of semiconductor substrate. Formation of a recessed polysilicon plug located in the bottom portion of the deep trench opening is followed by formation of an insulator plug located in a top portion of the deep trench opening, overlying the recessed polysilicon plug. This is accomplished via photolithographic and selective dry definition procedures, and a second chemical mechanical polishing procedure, resulting in a filled, deep trench opening exhibiting a smooth top surface topography.

    摘要翻译： 已经开发了用于形成由浅沟槽 - 深沟槽构造构成的隔离区域的工艺，其中获得用于隔离区域和半导体衬底中的相邻有源器件区域的平滑顶表面形貌。 该工艺特征最初形成通过第一化学机械抛光工艺平坦化的绝缘体填充的浅沟槽形状，允许在随后形成在绝缘体填充的浅沟槽形状中的窄直径，深沟槽开口期间实现降低的复杂性 半导体衬底的下面部分。 位于深沟槽开口底部的凹陷多晶硅插塞的形成之后，形成位于深沟槽开口的顶部的绝缘体塞，覆盖凹入的多晶硅插塞。 这通过光刻和选择性干法定义程序和第二化学机械抛光程序来实现，从而产生填充的深沟槽开口，表现出光滑的顶表面形貌。

    Elimination of implant damage during manufacture of HBT
    29.
    发明授权
    Elimination of implant damage during manufacture of HBT 有权
    在制造HBT期间消除植入物损伤

    公开(公告)号：US06847061B2

    公开(公告)日：2005-01-25

    申请号：US10406120

    申请日：2003-04-03

    申请人： Chun-Lin Tsai ,  Denny D. Tang ,  Chih-Min Chiang ,  Kuan-Lun Chang ,  Tsyr Shyang ,  Ruey-Hsin Liu

    发明人： Chun-Lin Tsai ,  Denny D. Tang ,  Chih-Min Chiang ,  Kuan-Lun Chang ,  Tsyr Shyang ,  Ruey-Hsin Liu

    IPC分类号： H01L21/331 ,  H01L29/10 ,  H01L29/737 ,  H01L31/0328 ,  H01L31/072

    CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

    摘要： During the conventional manufacture of HBTs, implant damage occurs which leads to enhanced internal base diffusion. This problem has been overcome by making the base and base contact area from a single, uniformly doped layer of silicon-germanium. Instead of an ion implant step to selectively reduce the resistance of this layer away from the base, a layer of polysilicon is selectively deposited (using selective epi deposition) onto only that part. Additionally, the performance of the polysilicon emitter is enhanced by means a brief thermal anneal that drives a small amount of opposite doping type silicon into the SiGe base layer.

    摘要翻译： 在常规制造HBT期间，会发生植入物损伤，导致内部基极扩散增强。 通过从单个均匀掺杂的硅 - 锗层制造基极和基极接触面积已经克服了该问题。 代替离子注入步骤来选择性地降低该层离开基极的电阻，选择性地沉积多晶硅层（使用选择性epi沉积）到该部分上。 此外，多晶硅发射极的性能通过将少量相反掺杂型硅驱动到SiGe基极层中的短暂的热退火来增强。

    High voltage transistor using P+ buried layer
    30.
    发明授权
    High voltage transistor using P+ buried layer 有权

    公开(公告)号：US06396126B1

    公开(公告)日：2002-05-28

    申请号：US09931318

    申请日：2001-08-17

    申请人： Jun-Lin Tsai ,  Ruey-Hsin Liu ,  Jyh-Min Jiang ,  Jei-Feng Hwang

    发明人： Jun-Lin Tsai ,  Ruey-Hsin Liu ,  Jyh-Min Jiang ,  Jei-Feng Hwang

    IPC分类号： H01L27082

    CPC分类号： H01L29/66272 ,  H01L29/0821 ,  H01L29/7392

    摘要： A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.