摘要:
Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of reconfigurable units that may include a plurality of processing elements (PEs) and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit. Each of the plurality of reconfigurable units may comprise a configuration buffer and a reconfiguration counter. The processor may further comprise a sequencer coupled to the configuration buffer of each of the plurality of reconfigurable units and configured to distribute a plurality of configurations to the plurality of reconfigurable units for the plurality of PEs and the plurality of MPs to execute a sequence of instructions.
摘要:
XPath evaluation in an XML data repository includes parsing an input XPath query using a simple path file to generate an execution tree about the XPath query, where the simple path file includes an XML file that is generated based on the hierarchical architecture of a plurality of XML files in the data repository, and the names of the nodes in the generated XML file are generated by recording the tag information of respective nodes in the plurality of XML files in the data repository. Execution of an execution tree for the data repository generates a final evaluation result.
摘要:
A method of transmitting data includes storing high-priority data blocks in a high-priority queue, storing low-priority data blocks in a low-priority queue, and generating a first data unit that includes one or more of the high-priority data blocks and one or more of the low-priority data blocks. Generating the first data unit includes arranging the one or more high-priority data blocks and the one or more low-priority data blocks in a sequence in which the one or more high-priority data blocks precede the one or more low-priority data blocks. Generating the first data unit further includes indexing the one or more high-priority data blocks and the one or more low-priority data blocks in accordance with the sequence. The first data unit is transmitted.
摘要:
Systems and methods for modeling the occurrence of common image components (e.g., sub-regions) in order to improve visual object recognition are disclosed. In one example, a query image may be matched to a training image of an object. A matched region within the training image to which the query image matches may be determined and a determination may be made whether the matched region is located within an annotated image component of the training image. When the matched region matches only to the image component, an annotation associated with the component may be identified. In another example, sub-regions within a plurality of training image corpora may be annotated as common image components including associated information (e.g., metadata). Matching sub-regions appearing in many training images of objects may be down-weighted in the matching process to reduce possible false matches to query images including common image components.
摘要:
Systems and methods for modeling the occurrence of common image components (e.g., sub-regions) in order to improve visual object recognition are disclosed. In one example, a query image may be matched to a training image of an object. A matched region within the training image to which the query image matches may be determined and a determination may be made whether the matched region is located within an annotated image component of the training image. When the matched region matches only to the image component, an annotation associated with the component may be identified. In another example, sub-regions within a plurality of training image corpora may be annotated as common image components including associated information (e.g., metadata). Matching sub-regions appearing in many training images of objects may be down-weighted in the matching process to reduce possible false matches to query images including common image components.
摘要:
Methods and apparatus for tail termination are provided that include a decoder that includes a processor configured to a forward state metric and a backward state metric wherein each iteration of an initial state of the backward state metric is fetched from a memory and is pre-computed without feedback from a decoding iteration. Each decoding iteration is substantially identical, and the backward state metric that is pre-computed is used for a subsequent iteration. The decoder may include a turbo decoder or a radix-4 decoder.
摘要:
Provided are devices, systems and methods for rate matching and de-rate matching on digital signal processors. In one embodiment, a device for rate matching and de-rate matching, includes an interface for receiving a plurality of blocks of data and digital signal processor configured to pre-compute permutation parameters common to the plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters and receive a set of pre-computed puncturing thresholds. For one or more blocks in the plurality of blocks, the DSP computes a block signature from the pre-computed puncturing thresholds; matches the block signature to one of a set of pre-computed zone signatures, derives a zone index corresponding to the one pre-computed zone signature, and applies pre-computed permutation and puncturing transformations corresponding to the zone index to the block.
摘要:
A circuit device is configured with robust circuit connectors. In connection with various example embodiments, an integrated circuit device includes one or more via network layers below a bond pad contact, connecting the bond pad contact with one or more underlying metal layers. Each via network layer includes a plurality of via strips extending about parallel to the bond pad contact and in different directions to structurally support the bond pad contact.
摘要:
Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.
摘要:
An exemplary liquid crystal display (400) includes a liquid crystal panel (430), a gate driving circuit (410), a data driving circuit (420), and a compensation circuit (440). The liquid crystal panel includes a plurality of gate lines (401) and a plurality of data lines (402) intersecting with the gate lines. The gate driving circuit is configured for providing a plurality of scanning signals to the gate lines in sequence. The data driving circuit is configured for providing a plurality of gray scale voltages to the data lines. The compensation circuit is configured for compensating the scanning signals. The compensation circuit is charged by alternate of the scanning signals, and discharges each such charge to provide a compensation signal to a gate line corresponding to a next scanning signal.