公开(公告)号：US20240329839A1

公开(公告)日：2024-10-03

申请号：US18190724

申请日：2023-03-27

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Tsun-Ho Liu ,  Anwar Parvez Kashem ,  Pouya Najafi Ashtiani ,  Gershom Birk ,  David Da Wei Lin

IPC: G06F3/06 ,  G06F1/08 ,  H04L7/00

CPC classification number: G06F3/0611 ,  G06F1/08 ,  G06F3/0656 ,  G06F3/0673 ,  H04L7/0016

Abstract: Clock domain phase adjustment techniques and systems for memory operations are described. In one example, a physical memory is communicatively coupled to a physical layer via a first clock domain and a memory controller is communicatively coupled to the physical layer via a second clock domain that is different than the first clock domain. A buffer is implemented in the physical layer. The buffer is configured to set a phase adjustment for a latency setting between the first and second clock domains. The phase adjustment is based on whether a mismatch has occurred in data output by the buffer to the memory controller based on a comparison to the latency setting.

公开(公告)号：US20240329833A1

公开(公告)日：2024-10-03

申请号：US18192694

申请日：2023-03-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Christopher J. Brennan ,  Akshay Lahiry ,  Guennadi Riguer

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0673

Abstract: Techniques for performing memory operations are disclosed herein. The techniques include generating a plurality of performance log entries based on observed operations; generating a plurality of memory access log entries based on the observed operations, wherein each performance log entry of the plurality of performance log entries are associated with one or more memory access log entries of the plurality of memory access log entries, wherein each performance log entry is associated with an epoch; and wherein each memory access log entry is associated with an epoch and a memory address range.

公开(公告)号：US12107076B2

公开(公告)日：2024-10-01

申请号：US17564137

申请日：2021-12-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Wonjun Jung ,  Jasmeet Singh Narang ,  Tyrone Huang ,  Christopher Klement ,  Alan D. Smith ,  Edward Chang ,  John Wuu

IPC: H01L25/065 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L25/0652 ,  H01L2225/06544

Abstract: Integrated circuits and integrated circuit dies include TSVs laid out in symmetrical patterns. Because of the symmetrical arrangement of the TSVs and associated routing patterns, an integrated circuit is able to support operation of multiple similar dies that are placed in different positions in the integrated circuit. This in turn simplifies the design and production of the multiple similar dies, thus reducing development and manufacturing costs for the corresponding integrated circuits.

公开(公告)号：US12105634B2

公开(公告)日：2024-10-01

申请号：US17486131

申请日：2021-09-27

Applicant: ATI TECHNOLOGIES ULC

Inventor： Edwin Pang ,  Jimshed Mirza

IPC: G06F12/10 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/68

Abstract: A processing system includes a translation lookaside buffer (TLB). The TLB includes a plurality of TLB entries that are configured to store requested page size indications. The TLB is configured to be indexed via the requested page size indications such that a plurality of TLB requests that each indicate a same virtual address, but different respective requested page sizes are allocated respective TLB entries. As a result, in response to a TLB request that indicates a requested page size and has a virtual address that corresponds to multiple TLB entries, only a single TLB entry is identified as a TLB hit.

公开(公告)号：US20240324248A1

公开(公告)日：2024-09-26

申请号：US18474179

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： John Wuu ,  Kevin Gillespie ,  Samuel Naffziger ,  Spence Oliver ,  Rajit Seahra ,  Regina T. Schmidt ,  Raja Swaminathan ,  Omar Zia

IPC: H10B80/00 ,  H01L23/544 ,  H01L25/00 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L23/544 ,  H01L25/18 ,  H01L25/50 ,  H01L23/481 ,  H01L23/5286 ,  H01L24/06 ,  H01L24/08 ,  H01L2223/54433 ,  H01L2224/06181 ,  H01L2224/08145

Abstract: A method for die pair partitioning can include providing a circuit die. The method can additionally include providing one or more additional circuit die having one or more fuses positioned therein, wherein the one or more fuses identify the circuit die. The method can also include connecting the one or more additional circuit die to the circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US12079642B2

公开(公告)日：2024-09-03

申请号：US15338492

申请日：2016-10-31

Applicant: ATI TECHNOLOGIES ULC

Inventor： Anthony W L Koo ,  Syed Athar Hussain

IPC: G06F9/44 ,  G06F9/4401 ,  G06F9/451 ,  G09G5/14 ,  G09G5/36 ,  G09G5/399

CPC classification number: G06F9/451 ,  G06F9/4411 ,  G09G5/14 ,  G09G5/363 ,  G09G5/399 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2340/0435 ,  G09G2340/14 ,  G09G2360/08 ,  G09G2360/18

Abstract: A system is provided that includes a computing device operable to render video content for display on a display device and to periodically refresh that display device. The video content includes at least one application window. A desktop compositor is operable to wake and execute commands to compose video frames that are composited surfaces that include the at least one application window and to initiate a buffer flip to deliver the video frames to the display device. A high resolution timer is operable to cause the desktop compositor to wake and execute the commands in multiple instances between display refreshes.

公开(公告)号：US20240289150A1

公开(公告)日：2024-08-29

申请号：US18113655

申请日：2023-02-24

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： Philip Ng ,  Nippon Raval ,  Jeremy W. Powell ,  Donald Matthews, JR. ,  David Kaplan

IPC: G06F9/455 ,  G06F13/42

CPC classification number: G06F9/45558 ,  G06F13/4221 ,  G06F2009/45579 ,  G06F2213/0026

Abstract: A processor includes a security processor and an input-output memory management unit (IOMMU). The security processor is configured to maintain device control information in a secure data structure and prevent a hypervisor from accessing the secure data structure. The IOMMU is configured to process at least one device request targeting a virtual machine from an input/output device based on the secure data structure.

公开(公告)号：US12047592B2

公开(公告)日：2024-07-23

申请号：US18447929

申请日：2023-08-10

Applicant: ATI Technologies ULC

Inventor： Konstantine Iourcha ,  Andrew S. C. Pomianowski

IPC: G06T9/00 ,  H04N19/119 ,  H04N19/154 ,  H04N19/176 ,  H04N19/182 ,  H04N19/426 ,  H04N19/46 ,  H04N19/54 ,  H04N19/60 ,  H04N19/96

CPC classification number: H04N19/426 ,  G06T9/00 ,  H04N19/119 ,  H04N19/154 ,  H04N19/176 ,  H04N19/182 ,  H04N19/46 ,  H04N19/54 ,  H04N19/60 ,  H04N19/96

Abstract: A system and method for texture decompression is described. The method comprises receiving a compressed texture block including two or more disjoint subsets of data and decompressing the compressed texture block. The decompressing includes decompressing each of the two or more disjoint subsets in the compressed texture block to form texels. The two or more disjoint subsets include a first disjoint subset having a first set of color endpoints and a first index value for a first texel, and a second disjoint subset having a second set of color endpoints.

公开(公告)号：US12045362B2

公开(公告)日：2024-07-23

申请号：US17889956

申请日：2022-08-17

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： Benjamin Koon Pan Chan ,  William Lloyd Atkinson ,  Tung Chuen Kwong ,  Guhan Krishnan

IPC: G06F21/62 ,  G06V10/94

CPC classification number: G06F21/6218 ,  G06V10/955

Abstract: A computer vision processor in an image cluster defines a fenced memory region (FMR) that controls access to image data stored in a first portion of a trusted memory region (TMR). The computer vision processor receives FMR requests from an application implemented in a processing cluster. The FMR requests are to access the image data in the first portion of the TMR. The computer vision processor selectively allows the requesting application to access the image data. In some cases, the computer vision processor acquires the image data and stores the image data in the first portion of the TMR, such as buffers in the TMR. A data fabric selectively permits the image processing application to access the data stored in the TMR based on whether the image cluster has opened or closed the FMR for the portion of the TMR.

公开(公告)号：US12045106B2

公开(公告)日：2024-07-23

申请号：US17564139

申请日：2021-12-28

Applicant: ATI TECHNOLOGIES ULC

Inventor： Yinan Jiang

IPC: G06F1/24 ,  G06F9/455 ,  G06F11/14

CPC classification number: G06F1/24 ,  G06F9/45558 ,  G06F11/1484 ,  G06F2009/45575 ,  G06F2201/815

Abstract: A virtual function (VF) of a virtual machine is enabled to directly reset a processing portion of a processing unit. The VF initiates the reset of the processing portion directly and a host driver associated with the processing unit is bypassed during the reset process. By allowing for a direct reset of the processing portion, a processing system reduces the overhead associated with the reset process, enhances system security, and improves overall VM and hardware isolation at the processing system.