公开(公告)号：US07294998B2

公开(公告)日：2007-11-13

申请号：US10538595

申请日：2003-12-12

Applicant: Noriaki Chiba

Inventor： Noriaki Chiba

IPC: G01R31/28

CPC classification number: G01R31/31922

Abstract: A timing generation circuit can increase a maximum delay amount without changing the configuration of a timing memory. The timing generation circuit includes: a timing memory (TMM) 10 containing predetermined timing data; a plurality of down counters 20 for loading the timing data from the TMM and outputting a pulse signal at the timing indicated by the timing data; an address selection circuit 40 for specifying one or two TMM addresses by switching and outputting corresponding one or plural timing data; a load data switching circuit 50 for loading the plural timing data to the plural down counters cascaded and outputting one timing pulse signal; and a timing data selection circuit 60 for selecting one of the pulse signals. The plural timing data are generated by dividing the timing memory into a plurality of memory regions either in a column or row direction.

Abstract translation: 定时生成电路可以在不改变定时存储器的配置的情况下增加最大延迟量。 定时产生电路包括：包含预定定时数据的定时存储器（TMM）10; 多个下降计数器20，用于从TMM加载定时数据，并在由定时数据指示的定时输出脉冲信号; 地址选择电路40，用于通过切换和输出相应的一个或多个定时数据来指定一个或两个TMM地址; 负载数据切换电路50，用于将多个定时数据加载到多个下拉计数器级联并输出一个定时脉冲信号; 以及用于选择脉冲信号之一的定时数据选择电路60。 通过将定时存储器分成列或行方向的多个存储区域来生成多个定时数据。

公开(公告)号：US07263150B2

公开(公告)日：2007-08-28

申请号：US10082563

申请日：2002-02-23

Applicant: Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

Inventor： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

IPC: H04L25/38 ,  H04D3/24

CPC classification number: G01R31/31937 ,  G01R31/31725

Abstract: A probability estimating apparatus and method for peak-to-peak clock skews for testing the clock skews among a plurality of clock signals distributed by a clock distributing circuit, and for estimating the generation probability of the peak-to-peak value or peak value of the clock skews. The probability estimating apparatus for peak-to-peak values in clock skews includes a clock skew estimator for estimating clock skew sequences among the plurality of clock signals under test and a probability estimator for determining a generation probability of the peak-to-peak values in the clock skews among the plurality of clock signals under test based on the clock skew sequences from the clock skew estimator by applying Rayleigh distribution. The generation probability of the peak-to-peak value is estimated based on RMS values of the clock signals and the Rayleigh distribution.

Abstract translation: 一种用于测试由时钟分配电路分配的多个时钟信号中的时钟偏差的峰 - 峰时钟偏差的概率估计装置和方法，并且用于估计峰 - 峰值或峰值的发生概率 时钟偏差。 用于时钟偏差中的峰 - 峰值的概率估计装置包括用于估计被测试的多个时钟信号之间的时钟偏移序列的时钟偏差估计器，以及用于确定在测试中的峰 - 峰值的生成概率的概率估计器 通过应用瑞利分布，基于来自时钟偏差估计器的时钟偏移序列，时钟在测试的多个时钟信号之间偏移。 基于时钟信号的RMS值和瑞利分布来估计峰峰值的发生概率。

公开(公告)号：US07187192B2

公开(公告)日：2007-03-06

申请号：US10512296

申请日：2003-04-21

Applicant: Hideyuki Oshima ,  Yasutaka Tsuruki

Inventor： Hideyuki Oshima ,  Yasutaka Tsuruki

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/02

CPC classification number: G01R31/31922

Abstract: A semiconductor test device for acquiring a multiplexed clock signal from LSI output data and using the clock to test the LSI. The device includes a time interpolator and registers connected in series. The time interpolator has flip-flops connected in parallel for receiving output data from an LSI under test, a delay circuit for successively inputting strobes delayed at a constant timing interval to the flip-flops and outputting time-series level data, and an encoder for receiving the time-series level data from the flip-flops and encoding it into position data indicating an edge timing. The registers successively store position data from the encoder and output them at a predetermined timing. The device further includes a digital filter for outputting the position data from the registers as a recovery clock.

Abstract translation: 一种用于从LSI输出数据获取多路复用时钟信号并使用时钟测试LSI的半导体测试装置。 该装置包括时间插值器和串联连接的寄存器。 时间插值器具有并联连接的触发器，用于接收来自被测LSI的输出数据，用于连续输入以恒定定时间隔延迟的选通脉冲并延迟触发器并输出时间序列电平数据的延迟电路，以及编码器 从触发器接收时间序列电平数据并将其编码成表示边沿定时的位置数据。 寄存器依次存储来自编码器的位置数据，并在预定的时刻输出。 该装置还包括用于从作为恢复时钟的寄存器输出位置数据的数字滤波器。

公开(公告)号：US07178115B2

公开(公告)日：2007-02-13

申请号：US10412143

申请日：2003-04-11

Applicant: Rochit Rajsuman ,  Hiroaki Yamoto

Inventor： Rochit Rajsuman ,  Hiroaki Yamoto

IPC: G06F17/50

CPC classification number: G01R31/318314 ,  G01R31/31704 ,  G01R31/31917 ,  G06F17/5022 ,  H01L27/118

Abstract: A manufacturing process for LSIs uses an event tester simulator and an event tester to avoid prototype hold. In the LSI manufacturing method an LSI is designed under an EDA (electronic design automation) environment to produce design data of a designed LSI, and logic simulation is performed on a device model of the LSI design in the EDA environment with use of a testbench and producing a test vector file of an event format as a result of the logic simulation. Then, simulation data files are verified with use of the design data and the testbench by operating an event tester simulator, and a prototype LSI is produced through a fabrication provider by using the design data. The prototype LSI is tested by an event tester by using the test vector file and the simulation data files and test results is feedbacked to the EDA environment or the fabrication provider.

Abstract translation: LSI的制造过程使用事件测试器模拟器和事件测试器来避免原型保持。 在LSI制造方法中，在EDA（电子设计自动化）环境下设计LSI以产生设计的LSI的设计数据，并且使用测试台在EDA环境中对LSI设计的设备模型进行逻辑模拟， 作为逻辑模拟的结果产生事件格式的测试向量文件。 然后，通过使用事件测试器模拟器，使用设计数据和测试平台验证仿真数据文件，并通过使用设计数据通过制造提供商生产原型LSI。 原型LSI由事件测试者通过​​使用测试矢量文件和仿真数据文件进行测试，测试结果反馈给EDA环境或制造商。

公开(公告)号：US07164141B2

公开(公告)日：2007-01-16

申请号：US11090244

申请日：2005-03-25

Applicant: Masaki Kurokawa

Inventor： Masaki Kurokawa

IPC: H01L21/027 ,  G03F7/20

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  H01J37/3174 ,  H01J2237/31793

Abstract: A charged particle beam photolithography machine includes an electron gun, a deflector, a wafer stage, a standard substrate formed with a chip-shaped first mark group having a plurality of first marks and a chip-shaped second mark group having a plurality of second marks, a correction map having misalignment factors of the first marks based on positions of the second marks, and a deflection control unit for controlling an amount of deflection in the deflector. The charged particle is irradiated on a wafer while the deflection control unit makes reference to the correction map and corrects the amount of deflection as equivalent to the misalignment factors.

Abstract translation: 带电粒子束光刻机包括电子枪，偏转器，晶片台，形成有具有多个第一标记的芯片形状的第一标记组的标准基板和具有多个第二标记的芯片形状的第二标记组 ，具有基于第二标记的位置的第一标记的偏移因子的校正图以及用于控制偏转器中的偏转量的偏转控制单元。 当偏转控制单元参考校正图并且校正与不对准因子相当的偏转量时，将带电粒子照射在晶片上。

公开(公告)号：US07126366B2

公开(公告)日：2006-10-24

申请号：US10516093

申请日：2003-06-10

Applicant: Masatoshi Ohashi ,  Toshiyuki Okayasu

Inventor： Masatoshi Ohashi ,  Toshiyuki Okayasu

IPC: G01R31/02 ,  G01R31/28 ,  G01R31/26

CPC classification number: G01R31/31937 ,  G01R31/3191 ,  G01R31/31922

Abstract: Good device PASS/FAIL determination is realized by measuring timings of both signals, i.e., a cross point of differential clock signals CLK and a data signal DATA output from a DUT, and obtaining a relative phase difference between both signals. A semiconductor test apparatus comprises differential signal timing measurement means for outputting cross point information Tcross obtained by measuring a timing of a cross point of one of differential signals output from the device under test, non-differential signal timing measurement means for outputting data change point information Tdata obtained by measuring a timing of transition of a logic of the other non-differential signal output from the DUT, phase difference calculation means for outputting a phase difference ΔT obtained by calculating a relative phase difference between the cross point information Tcross and the data change point information Tdata obtained by simultaneously measuring both of the output signals, and PASS/FAIL determination means for determining PASS/FAIL of a relative positional relation of the DUT based on a predetermined threshold value for executing PASS/FAIL determination upon reception of the phase difference ΔT.

Abstract translation: 通过测量两个信号的时序，即差分时钟信号CLK的交叉点和从DUT输出的数据信号DATA，并获得两个信号之间的相对相位差来实现良好的设备PASS / FAIL确定。 半导体测试装置包括：差分信号定时测量装置，用于输出通过测量从被测器件输出的差分信号之一的交叉点的定时获得的交叉点信息Tcross;非差分信号定时测量装置，用于输出数据变化点信息 Tdata通过测量从DUT输出的另一个非差分信号的逻辑的转换的定时获得的相位差计算装置，用于输出通过计算交叉点信息Tcross和数据变化之间的相对相位差而获得的相位差DeltaT 通过同时测量两个输出信号获得的点信息Tdata和用于根据接收到相位差执行PASS / FAIL确定的预定阈值来确定DUT的相对位置关系的PASS / FAIL的PASS / FAIL确定装置 DeltaT。

公开(公告)号：US07098680B2

公开(公告)日：2006-08-29

申请号：US10800189

申请日：2004-03-12

Applicant: Kentaro Fukushima ,  Masashi Hoshino

Inventor： Kentaro Fukushima ,  Masashi Hoshino

IPC: G01R31/02

CPC classification number: G01R31/2889 ,  G01R31/31905 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: A connection unit for electrically connecting a DUT mounting board, on which an IC socket is mounted, with a testing apparatus for testing an electronic device inserted into the IC socket, the connection unit has a holding substrate provided to face the DUT mounting board and a connection-unit-side connector, which is provided on the holding substrate to be able to change a position of the connection-unit-side connector on the holding substrate, for being connected to a performance-board-side connector included in the DUT mounting board.

公开(公告)号：US07068086B2

公开(公告)日：2006-06-27

申请号：US10484984

申请日：2002-07-26

Applicant: Akihiro Takeda

Inventor： Akihiro Takeda

IPC: H03L7/00

CPC classification number: H04L7/02 ,  H04L7/0041

Abstract: There is provided a phase correction circuit capable of detecting a skew between a data signal and a clock signal without requiring a clock signal as pattern data upon initialization. The phase correction circuit is configured to include a variable delay device 10 to which a data signal in a DDR format is inputted, a first F/F 1 which fetches a delayed data signal in synchronization with the clock signal, a second F/F 2 which fetches the delayed data signal in synchronization with a reverse clock signal, a third F/F 3 which fetches an output signal from the first F/F 1 in synchronization with the clock signal, and a fourth F/F 4 which fetches an output signal from the second F/F 2 in synchronization with the clock signal, and the phase correction circuit further includes a fifth F/F 5 which fetches a rate signal having the same cycle as that of the data signal in synchronization with the clock signal, a sixth F/F 6 which fetches an output signal from the fifth F/F 5 in synchronization with the clock signal, and an AND circuit 8 to which an output signal from the third F/F 3 and an output signal from the sixth F/F 6 are inputted.

Abstract translation: 提供了一种相位校正电路，能够检测数据信号和时钟信号之间的偏差，而不需要在初始化时作为模式数据的时钟信号。 相位校正电路被配置为包括：可变延迟装置10，以DDR格式输入数据信号;第一F / F 1，其与时钟信号同步地取出延迟的数据信号;第二F / F 2 其与反向时钟信号同步地取出延迟的数据信号;第三F / F 3，其与时钟信号同步地从第一F / F 1取出输出信号;以及第四F / F 4，其取出输出 来自第二F / F 2的信号与时钟信号同步，并且相位校正电路还包括第五F / F 5，其与时钟信号同步地取出具有与数据信号相同的周期的速率信号， 与时钟信号同步地从第五F / F 5取出输出信号的第六F / F 6和来自第三F / F 3的输出信号和来自第六F的输出信号的“与”电路8 / F 6。

公开(公告)号：US07027217B2

公开(公告)日：2006-04-11

申请号：US10381575

申请日：2001-10-11

Applicant: Eiji Kanou

Inventor： Eiji Kanou

IPC: H04B10/12

CPC classification number: H01S3/06791

Abstract: An optical pulse testing apparatus incorporating an optical pulse generator composed of low cost components. The optical pulse testing apparatus comprises: a ring optical path including an optical fiber 30 with a rare earth element added to; an excitation light source 32 which enters excitation optical pulses into the optical fiber 30; an optical branching filter 38 for branching the circulating optical pulses circulating through the ring optical path to emit output optical pulses; and a photodetector 40 for detecting the circulating optical pulses circulating through the ring optical path to obtain signals indicative of a light intensity and a generation timing of the circulating optical pulses. Thus, the optical pulse generator, and the optical pulse testing apparatus and method using the optical pulse generator require no expensive optical parts and complicated device control.

Abstract translation: 一种包含由低成本组件组成的光脉冲发生器的光脉冲测试装置。 光脉冲测试装置包括：环形光路，包括添加有稀土元素的光纤30; 激发光源32，其将激发光脉冲输入到光纤30中; 光分路滤波器38，用于对通过环形光路循环的循环光脉冲进行分支以发射输出光脉冲; 以及光检测器40，用于检测通过环形光路循环的循环光脉冲，以获得指示循环光脉冲的光强度和产生定时的信号。 因此，光脉冲发生器和使用光脉冲发生器的光脉冲测试装置和方法不需要昂贵的光学部件和复杂的装置控制。

公开(公告)号：US20030090259A1

公开(公告)日：2003-05-15

申请号：US10326392

申请日：2002-12-23

Applicant: ADVANTEST CORP.

Inventor： James Warren Frame

IPC: G01R001/00

CPC classification number: G01R31/2886 ,  G01R1/07378

Abstract: In order to form a modular interface between a DUT board, which is housing devices under tests (DUT), to cables connected to a test head, a board spacer is provided that has an array of connectors. Each cable is connected to a respective connector, and the DUT board contains a corresponding array of connection points which are less than or equal to the number of connectors in the arrays on the board spacer. In this way, a common board spacer can be used to connect the cables to DUT boards housing different types of DUTs since the location of the connection points on the board spacer is known and kept constant. This interface allows a high speed and high fidelity connection between the test head and the devices on the DUTs for frequencies in excess of 50 MHz.