Semiconductor packages and related methods

    公开(公告)号:US12062549B2

    公开(公告)日:2024-08-13

    申请号:US17304792

    申请日:2021-06-25

    摘要: Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.

    Image Sensors with Extended Dynamic Range
    23.
    发明公开

    公开(公告)号:US20240259705A1

    公开(公告)日:2024-08-01

    申请号:US18360972

    申请日:2023-07-28

    发明人: Sergey VELICHKO

    IPC分类号: H04N25/571 H04N25/78

    CPC分类号: H04N25/571 H04N25/78

    摘要: An image sensor may include an array of imaging pixels arranged in rows and columns. A method of operating an imaging pixel is provided that includes accumulating charge in a photosensitive element, allowing the accumulated charge in the photodiode to overflow into a capacitor that is coupled to a reset transistor having a gate terminal configured to receive a reset control signal during an integration phase, and extending the dynamic range of the imaging pixel by dynamically adjusting the reset control signal from a first voltage level to a second voltage level during the integration phase. The reset control signal can be lowered from the first voltage level to the second voltage level in a discrete or continuous fashion such that a portion of the overflow charge in the capacitor represents a linear signal and a portion of the overflow charge in the capacitor represents a non-linear signal.

    SINGULATION OF SILICON CARBIDE SEMICONDUCTOR WAFERS

    公开(公告)号:US20240234155A1

    公开(公告)日:2024-07-11

    申请号:US18613913

    申请日:2024-03-22

    IPC分类号: H01L21/304 H01L29/16

    摘要: A method of singulating a silicon carbide (SiC) semiconductor wafer can include defining a cut within the silicon carbide (SiC) semiconductor wafer by performing a partial dicing operation where the SiC semiconductor wafer is aligned along a plane and the cut has a depth less than a first thickness of the SiC semiconductor wafer. The cut is aligned along a vertical direction orthogonal to the plane such that a portion of the SiC semiconductor wafer has a second thickness that extends between a bottom of the cut and an outer surface of the SiC semiconductor wafer. The method can further include defining a cleave, by performing a cleaving operation, through the portion of the SiC semiconductor wafer having the second thickness. The cleave can be aligned with the cut and extending to the outer surface of the SiC semiconductor wafer.

    Methods and apparatus for driver calibration

    公开(公告)号:US12015381B2

    公开(公告)日:2024-06-18

    申请号:US18450123

    申请日:2023-08-15

    发明人: Seiji Takeuchi

    摘要: Driver circuits, systems for driving actuators, and imaging systems with actuators. The driver circuit includes a current comparator circuit, a driver, and a replica circuit. The current comparator circuit includes a first node having a first voltage. The current comparator circuit also includes a second node having a second voltage. The driver includes a first terminal responsive to the second voltage. The driver also includes a second terminal connected to a reference voltage. The replica circuit includes a third terminal connected to the first node. The replica circuit also includes a fourth terminal connected to the second terminal of the driver. The replica circuit also includes a fifth terminal connected to the first terminal of the driver.

    EDGE SEALS FOR SEMICONDUCTOR PACKAGES
    30.
    发明公开

    公开(公告)号:US20240194710A1

    公开(公告)日:2024-06-13

    申请号:US18586731

    申请日:2024-02-26

    IPC分类号: H01L27/146

    摘要: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.