公开(公告)号：US09898306B2

公开(公告)日：2018-02-20

申请号：US15396726

申请日：2017-01-02

Applicant: Intel Corporation

Inventor： Michael Rothman ,  Robert Gough ,  Mark Doran

IPC: G06F1/26 ,  G06F9/44

CPC classification number: G06F9/4403 ,  G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/22 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/384 ,  G06F9/44 ,  G06F9/4401 ,  G06F9/4418 ,  G06F9/445 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3447 ,  G06F11/3466 ,  G06F11/3664 ,  G06F11/3672 ,  G06F11/3688 ,  G06F15/7871 ,  G06F17/30339 ,  G06F2209/501 ,  G06F2217/78 ,  Y02D10/126 ,  Y02D10/172

Abstract: In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data.

公开(公告)号：US09596136B2

公开(公告)日：2017-03-14

申请号：US14157948

申请日：2014-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangdok Mo ,  Sungmin Lee

IPC: G06F15/173 ,  H04L12/24 ,  G06F11/14 ,  G06F9/22 ,  G06F9/00 ,  G06F9/30 ,  G06F9/44 ,  G06F9/455 ,  H04L12/26

CPC classification number: H04L41/082 ,  G06F8/76 ,  G06F9/00 ,  G06F9/22 ,  G06F9/30 ,  G06F9/44 ,  G06F9/455 ,  G06F11/1402 ,  G06F11/1433 ,  H04L43/0894

Abstract: A software migration method and an apparatus for migration of software running at a source node to a destination node with a migration scheme selected optimally in consideration of micro-server communication environment are provided. The software migration apparatus includes an environment monitor which monitors communication environment between a source node and a destination node constituting a micro-server and a migration policy manager which analyzes communication environment information acquired from the environment monitor and determines a migration scheme for migrating a software running at the source node to the destination node based on the analysis result.

Abstract translation: 提供了一种考虑到微服务器通信环境，优选地选择在源节点处运行的软件迁移到具有迁移方案的目的地节点的软件迁移方法和装置。 软件迁移装置包括监视源节点与构成微服务器的目的地节点之间的通信环境的环境监视器以及分析从环境监视器获取的通信环境信息的迁移策略管理器，并且确定用于迁移正在运行的软件的迁移方案 在源节点根据分析结果到目标节点。

公开(公告)号：US20170068298A1

公开(公告)日：2017-03-09

申请号：US15354018

申请日：2016-11-17

Applicant: INTEL CORPORATION

Inventor： Michael Mishaeli ,  Ron Gabor ,  Robert C. Valentine ,  Alex Gerber ,  Zeev Sperber

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3287 ,  G06F9/22 ,  Y02D10/171

Abstract: Technologies for local power gate (LPG) interfaces for power-aware operations are described. A system on chip (SoC) includes a first functional unit, a second functional unit, and local power gate (LPG) hardware coupled to the first functional unit and the second functional unit. The LPG hardware is to power gate the first functional unit according to local power states of the LPG hardware. The second functional unit decodes a first instruction to perform a first power-aware operation of a specified length, including computing an execution code path for execution. The second functional unit monitors a current local power state of the LPG hardware, selects a code path based on the current local power state, the specified length, and a specified threshold, and issues a hint to the LPG hardware to power up the first functional unit and continues execution of the first power-aware operation without waiting for the first functional unit to be powered up.

Abstract translation: 描述了用于功率感知操作的本地电源门（LPG）接口的技术。 片上系统（SoC）包括耦合到第一功能单元和第二功能单元的第一功能单元，第二功能单元和本地电源门（LPG）硬件。 LPG硬件根据LPG硬件的本地电源状态为第一个功能单元供电。 第二功能单元解码执行指定长度的第一功率感知操作的第一指令，包括计算用于执行的执行代码路径。 第二功能单元监视LPG硬件的当前本地电源状态，根据当前本地电源状态，指定长度和指定的阈值选择代码路径，并向LPG硬件发出提示，以启动第一个功能 并且继续执行第一功率感知操作，而不等待第一功能单元被加电。

公开(公告)号：US09405601B2

公开(公告)日：2016-08-02

申请号：US14419016

申请日：2012-12-20

Applicant: Masuo Ito ,  Isamu Kawakami ,  Yoshiaki Katayama

Inventor： Masuo Ito ,  Isamu Kawakami ,  Yoshiaki Katayama

IPC: G06F13/00 ,  G06F9/54 ,  G06F13/42

CPC classification number: G06F9/544 ,  F02D1/00 ,  G05B15/00 ,  G05B19/00 ,  G06F9/22 ,  G06F9/44 ,  G06F13/4221

Abstract: An ASL is associated with an APP module having as a communication target an existing APP SW-C(1). A buffer part accumulates data to the existing APP SW-C(1) and data from the existing APP SW-C(1). A communication processing part transmits the data to the existing APP SW-C(1) accumulated in the buffer part to the existing APP SW-C(1), receives data transmitted from the existing APP SW-C(1), and stores the received data in the buffer part. An API processing part receives as input from the APP module data to the existing APP SW-C(1), stores the data received as input in the buffer part, receives as input from the buffer part data from the existing APP SW-C(1), and outputs the data received as input to the APP module.

Abstract translation: ASL与具有作为通信对象的现有APP SW-C（1）的APP模块相关联。 缓冲部分将现有APP SW-C（1）的数据和现有的APP SW-C（1）的数据进行累加。 通信处理部将数据发送到现有的APP SW-C（1）中，存储在缓冲部分中的现有APP SW-C（1），接收从现有的APP SW-C（1）发送的数据， 在缓冲部分接收数据。 API处理部分从APP模块数据接收到现有的APP SW-C（1），将作为输入接收的数据存储在缓冲器部分中，从来自现有APP SW-C的缓冲器部分数据中接收作为输入 1），并将作为输入接收的数据输出到APP模块。

公开(公告)号：US09280352B2

公开(公告)日：2016-03-08

申请号：US13307969

申请日：2011-11-30

Applicant: Ramesh B. Gunna ,  Peter J. Bannon ,  Rajat Goel

Inventor： Ramesh B. Gunna ,  Peter J. Bannon ,  Rajat Goel

IPC: G06F9/22 ,  G06F9/28 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/22 ,  G06F9/28 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3814

Abstract: An apparatus and method for avoiding bubbles and maintaining a maximum instruction throughput rate when cracking microcode instructions. A lookahead pointer scans the newest entries of a dispatch queue for microcode instructions. A detected microcode instruction is conveyed to a microcode engine to be cracked into a sequence of micro-ops. Then, the sequence of micro-ops is placed in a queue, and when the original microcode instruction entry in the dispatch queue is selected for dispatch, the sequence of micro-ops is dispatched to the next stage of the processor pipeline.

Abstract translation: 一种用于在破解微代码指令时避免气泡并保持最大指令吞吐率的装置和方法。 先行指针扫描调度队列的最新条目以获取微代码指令。 检测到的微代码指令被传送到微代码引擎以被破解成微操作序列。 然后，将微操作序列放置在队列中，并且当调度队列中的原始微代码指令条目被选择用于分派时，微操作序列被分派到处理器管线的下一个阶段。

公开(公告)号：US09135003B2

公开(公告)日：2015-09-15

申请号：US12987391

申请日：2011-01-10

Applicant: Dong-Kwan Suh ,  Hyeong-Seok Yu ,  Suk-Jin Kim

Inventor： Dong-Kwan Suh ,  Hyeong-Seok Yu ,  Suk-Jin Kim

IPC: G06F9/44 ,  G06F9/22 ,  G06F15/78 ,  G06F15/76

CPC classification number: G06F9/22 ,  G06F15/76 ,  G06F15/7867

Abstract: A reconfigurable processor for efficiently performing a vector operation, and a method of controlling the reconfigurable processor are provided. The reconfigurable processor designates at least one of a plurality of processing elements as a vector lane based on vector lane configuration information, and allocates a vector operation to the designated vector lane.

Abstract translation: 提供了一种用于有效执行向量操作的可重构处理器，以及一种控制可重构处理器的方法。 可重配置处理器基于向量车道配​​置信息将多个处理元件中的至少一个指定为向量车道，并且向指定的向量车道分配向量操作。

公开(公告)号：US09122465B2

公开(公告)日：2015-09-01

申请号：US13311809

申请日：2011-12-06

Applicant: Paul E. Schardt ,  Robert A. Shearer ,  Matthew R. Tubbs

Inventor： Paul E. Schardt ,  Robert A. Shearer ,  Matthew R. Tubbs

IPC: G06F9/22 ,  G06F9/38 ,  G06F9/24 ,  G06F9/32

CPC classification number: G06F9/22 ,  G06F9/24 ,  G06F9/328 ,  G06F9/3851

Abstract: A method and circuit arrangement utilize a programmable microcode unit that is capable of being programmed via software to modify the instruction sequences output by the microcode unit in response to microcode instructions issued to the microcode unit. Multiple instruction sequences may be stored in different partitions defined in one or more rewriteable memories such that different instruction sequences may be output for different instances of a microcode instruction executing in different, concurrently-executing instruction streams.

Abstract translation: 一种方法和电路装置利用可编程的微码单元，该可编程微码单元能够通过软件进行编程，以便响应于发出到微代码单元的微码指令来修改由微代码单元输出的指令序列。 多个指令序列可以存储在一个或多个可重写存储器中定义的不同分区中，以便可以针对在不同的并发执行的指令流中执行的微代码指令的不同实例输出不同的指令序列。

公开(公告)号：US20150212828A1

公开(公告)日：2015-07-30

申请号：US14126886

申请日：2013-10-24

Applicant: Intel Corporation

Inventor： Vincent J. Zimmer ,  Michael A. Rothman ,  Robert B. Bahnsen ,  Robert C. Swanson

IPC: G06F9/445 ,  G06F21/57

CPC classification number: G06F9/445 ,  G06F8/52 ,  G06F8/65 ,  G06F8/654 ,  G06F9/22 ,  G06F9/24 ,  G06F9/4403 ,  G06F9/4411 ,  G06F9/45516 ,  G06F21/572 ,  G06F21/575 ,  G06F2221/033

Abstract: Methods and apparatus relating to pre-OS (pre Operating System) image rewriting to provide cross-architecture support, security introspection, and/or performance optimization are described. In an embodiment, logic rewrites a non-native firmware interface driver into a native firmware interface driver in response to a determination that sufficient space is available in an integrity cache storage device to store the native firmware interface driver. The logic rewrites the non-native firmware interface driver into the native firmware interface driver by performing one or more of its operations during operating system runtime. Other embodiments are also claimed and described.

Abstract translation: 描述与前OS（预操作系统）图像重写相关以提供交叉架构支持，安全内省和/或性能优化的方法和装置。 在一个实施例中，响应于在完整性高速缓存存储设备中有足够的空间可用于存储本机固件接口驱动程序的确定，逻辑将非本地固件接口驱动程序重写为本机固件接口驱动程序。 逻辑通过在操作系统运行时执行其一个或多个操作，将非本地固件接口驱动程序重写为本机固件接口驱动程序。 还要求保护和描述其它实施例。

公开(公告)号：US20110154349A1

公开(公告)日：2011-06-23

申请号：US12641001

申请日：2009-12-17

Applicant: Andrew C. Walton ,  Jeffrey A. Barlow ,  Howard Calkin

Inventor： Andrew C. Walton ,  Jeffrey A. Barlow ,  Howard Calkin

IPC: G06F9/50

CPC classification number: G06F9/5061 ,  G06F9/22 ,  G06F9/44

Abstract: In accordance with at least some embodiments, a system includes a plurality of partitions, each partition having its own operating system (OS) and workload. The system also includes a plurality of resources assignable to the plurality of partitions. The system also includes management logic coupled to the plurality of partitions and the plurality of resources. The management logic is configured to set priority rules for each of the plurality of partitions based on user input. The management logic performs automated resource fault management for the resources assigned to the plurality of partitions based on the priority rules.

Abstract translation: 根据至少一些实施例，系统包括多个分区，每个分区具有其自己的操作系统（OS）和工作负载。 该系统还包括可分配给多个分区的多个资源。 该系统还包括耦合到多个分区和多个资源的管理逻辑。 管理逻辑被配置为基于用户输入来为多个分区中的每一个设置优先权规则。 管理逻辑基于优先级规则对分配给多个分区的资源执行自动资源故障管理。

公开(公告)号：US20100100712A1

公开(公告)日：2010-04-22

申请号：US12252541

申请日：2008-10-16

Applicant: Eric Oliver Mejdrich ,  Adam James Muff ,  Matthew Ray Tubbs

Inventor： Eric Oliver Mejdrich ,  Adam James Muff ,  Matthew Ray Tubbs

IPC: G06F9/30

CPC classification number: G06F9/3885 ,  G06F9/22 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/3867

Abstract: A processing unit includes multiple execution units and sequencer logic that is disposed downstream of instruction buffer logic, and that is responsive to a sequencer instruction present in an instruction stream. In response to such an instruction, the sequencer logic issues a plurality of instructions associated with a long latency operation to one execution unit, while blocking instructions from the instruction buffer logic from being issued to that execution unit. In addition, the blocking of instructions from being issued to the execution unit does not affect the issuance of instructions to any other execution unit, and as such, other instructions from the instruction buffer logic are still capable of being issued to and executed by other execution units even while the sequencer logic is issuing the plurality of instructions associated with the long latency operation.

Abstract translation: 处理单元包括多个执行单元和定序器逻辑，其布置在指令缓冲器逻辑的下游，并且响应于指令流中存在的定序器指令。 响应于这样的指令，定序器逻辑向一个执行单元发出与长等待时间操作相关联的多个指令，同时阻止来自指令缓冲器逻辑的指令被发送到该执行单元。 此外，指令的阻塞被发布到执行单元不影响向任何其他执行单元发出指令，因此来自指令缓冲器逻辑的其他指令仍然能够被发出并由其他执行执行 即使当定序器逻辑发出与长延迟操作相关联的多个指令时。