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    ARRAY OF CARBON NANOTUBE MICRO-TIP STRUCTURES
    21.
    发明申请
    ARRAY OF CARBON NANOTUBE MICRO-TIP STRUCTURES 有权
    碳纳米管微型结构阵列

    公开(公告)号：US20160329184A1

    公开(公告)日：2016-11-10

    申请号：US15214779

    申请日：2016-07-20

    Applicant: Tsinghua University ,  HON HAI PRECISION INDUSTRY CO., LTD.

    Inventor： YANG WEI ,  SHOU-SHAN FAN

    IPC: H01J1/14 ,  H01J1/304 ,  H01J9/04

    CPC classification number: H01J1/14 ,  H01J1/3044 ,  H01J9/042 ,  H01J37/073 ,  H01J63/02 ,  H01J63/06 ,  H01J2201/196 ,  H01J2201/30411 ,  H01J2201/30469 ,  H01J2237/06316 ,  H01J2237/06333 ,  H01J2237/06341 ,  H01J2237/26 ,  H01J2237/28 ,  H01J2329/0455 ,  Y10T428/24132

    Abstract: An array of carbon nanotube micro-tip structure includes an insulating substrate and a plurality of patterned carbon nanotube film structures. The insulating substrate includes a surface. The surface includes an edge. A plurality of patterned carbon nanotube film structures spaced from each other. Each of the plurality of patterned carbon nanotube film structures is partially arranged on the surface of the insulating substrate. Each of the plurality of patterned carbon nanotube film structures comprises two strip-shaped arms joined together forming a tip portion protruding and suspending from the edge of the surface of the insulating substrate. Each of the two strip-shaped arms comprises a plurality of carbon nanotubes parallel to the surface of the insulating substrate.

    Abstract translation: 碳纳米管微尖端结构的阵列包括绝缘基板和多个图案化的碳纳米管薄膜结构。 绝缘基板包括表面。 表面包括边缘。 多个图案化的碳纳米管薄膜结构彼此间隔开。 多个图案化碳纳米管膜结构中的每一个部分地布置在绝缘基板的表面上。 多个图案化碳纳米管膜结构中的每一个包括两个连接在一起的条形臂，形成从绝缘基板的表面的边缘突出并悬挂的末端部分。 两个条形臂中的每一个包括平行于绝缘基板的表面的多个碳纳米管。

    Method for producing a field-emitter array with controlled apex sharpness
    22.
    发明授权
    Method for producing a field-emitter array with controlled apex sharpness 有权
    制造具有受控顶尖锐度的场发射器阵列的方法

    公开(公告)号：US08216863B2

    公开(公告)日：2012-07-10

    申请号：US13001449

    申请日：2009-05-29

    Applicant: Eugenie Kirk ,  Soichiro Tsujino

    Inventor： Eugenie Kirk ,  Soichiro Tsujino

    IPC: H01L21/00 ,  H01L21/331

    CPC classification number: H01J9/025 ,  H01J1/3044 ,  H01J2201/30411 ,  H01J2209/0223

    Abstract: A method of manufacturing field-emitter arrays by a molding technique includes uniformly controlling a shape of mold holes to obtain field emitter tips having diameters below 100 nm and blunted side edges. Repeated oxidation and etching of a mold substrate formed of single-crystal semiconductor mold wafers is carried out, wherein the mold holes for individual emitters are fabricated by utilizing the crystal orientation dependence of the etching rate.

    Abstract translation: 通过模制技术制造场致发射器阵列的方法包括均匀地控制模具孔的形状以获得直径小于100nm的场发射器尖端和钝化的侧边缘。 进行由单晶半导体模具晶片形成的模具基板的重复氧化和蚀刻，其中通过利用蚀刻速率的晶体取向依赖性来制造各个发光体的模具孔。

    DIAMOND ELECTRON SOURCE AND METHOD FOR MANUFACTURING THE SAME
    23.
    发明申请
    DIAMOND ELECTRON SOURCE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    金刚石电子源及其制造方法

    公开(公告)号：US20090160307A1

    公开(公告)日：2009-06-25

    申请号：US12094250

    申请日：2007-09-18

    Applicant: Akihiko Ueda ,  Yoshiyuki Yamamoto ,  Yoshiki Nishibayashi ,  Takahiro Imai

    Inventor： Akihiko Ueda ,  Yoshiyuki Yamamoto ,  Yoshiki Nishibayashi ,  Takahiro Imai

    IPC: H01J1/16 ,  H01J9/02

    CPC classification number: H01J1/3044 ,  H01J9/025 ,  H01J37/065 ,  H01J37/073 ,  H01J2201/30407 ,  H01J2201/30411 ,  H01J2201/30419 ,  H01J2201/30457 ,  H01J2237/06341 ,  H01J2237/26 ,  H01J2237/3137 ,  H01J2237/3146 ,  H01J2237/31749 ,  H01J2237/3175

    Abstract: A diamond electron source in which a single sharpened tip is formed at one end of a pillar-shaped diamond monocrystal of a size for which resist application is difficult in a microfabrication process, as an electron emission point used in an electron microscope or other electron beam device, and a method for manufacturing the diamond electron source. One end of a pillar-shaped diamond monocrystal 10 is ground to form a smooth flat surface 11, and a ceramic layer 12 is formed on the smooth flat surface 11. A thin-film layer 14 having a prescribed shape is deposited on the ceramic layer 12 using a focused ion beam device, after which the ceramic layer 12 is patterned by etching using the thin-film layer 14 as a mask. A single sharpened tip is formed at one end of the pillar-shaped diamond monocrystal 10 by dry etching using the resultant ceramic mask.

    Abstract translation: 一种金刚石电子源，其中在微细加工过程中难以施加抗蚀剂尺寸的柱状金刚石单晶的一端形成单个锐化尖端作为电子显微镜或其他电子束中使用的电子发射点 器件，以及金刚石电子源的制造方法。 将柱状金刚石单晶10的一端研磨成平滑的平坦面11，在平坦的平坦面11上形成陶瓷层12.具有规定形状的薄膜层14沉积在陶瓷层上 12，使用聚焦离子束装置，之后通过使用薄膜层14作为掩模的蚀刻对陶瓷层12进行图案化。 通过使用所得到的陶瓷掩模的干蚀刻，在柱状金刚石单晶10的一端形成单个尖锐的尖端。

    SELF-ALIGNED GATED EMITTER TIP ARRAYS
    26.
    发明申请
    SELF-ALIGNED GATED EMITTER TIP ARRAYS 审中-公开
    自对准浇口发射器提升阵列

    公开(公告)号：US20160254114A1

    公开(公告)日：2016-09-01

    申请号：US14935993

    申请日：2015-11-09

    Applicant: Massachusetts Institute of Technology

    Inventor： Arash Akhavan Fomani ,  Luis Fernando Velasquez-Garcia ,  Akintunde I. Akinwande

    IPC: H01J9/02 ,  H01J1/304

    CPC classification number: H01J9/025 ,  H01J1/304 ,  H01J2201/30411 ,  H01L21/00 ,  H01T19/04 ,  H01T23/00

    Abstract: Methods for fabrication of self-aligned gated tip arrays are described. The methods are performed on a multilayer structure that includes a substrate, an intermediate layer that includes a dielectric material disposed over at least a portion of the substrate, and at least one gate electrode layer disposed over at least a portion of the intermediate layer. The method includes forming a via through at least a portion of the at least one gate electrode layer. The via through the at least one gate electrode layer defines a gate aperture. The method also includes etching at least a portion of the intermediate layer proximate to the gate aperture such that an emitter structure at least partially surrounded by a trench is formed in the multilayer structure.

    Abstract translation: 描述了自对准浇口尖端阵列的制造方法。 该方法在包括衬底，包括设置在衬底的至少一部分上的电介质材料的中间层以及设置在中间层的至少一部分上的至少一个栅电极层的多层结构上进行。 该方法包括通过至少一个栅极电极层的至少一部分形成通孔。 通过至少一个栅极电极层的通孔限定栅极孔径。 该方法还包括蚀刻靠近栅极孔的中间层的至少一部分，使得在多层结构中形成至少部分被沟槽包围的发射极结构。

    Ion source with cathode having an array of nano-sized projections
    28.
    发明授权
    Ion source with cathode having an array of nano-sized projections 有权
    具有阴极的离子源具有纳米尺寸的突起阵列

    公开(公告)号：US08866068B2

    公开(公告)日：2014-10-21

    申请号：US13728950

    申请日：2012-12-27

    Applicant: Schlumberger Technology Corporation

    Inventor： Jani Reijonen ,  Luke Perkins ,  Harold Pfutzner

    IPC: G01V5/00 ,  H01J27/20 ,  G01V5/08

    CPC classification number: H01J27/205 ,  G01V5/085 ,  H01J1/3044 ,  H01J3/04 ,  H01J2201/30411

    Abstract: An ion source for use in a particle accelerator includes at least one cathode. The at least one cathode has an array of nano-sized projections and an array of gates adjacent the array of nano-sized projections. The array of nano-sized projections and the array of gates have a first voltage difference such that an electric field in the cathode causes electrons to be emitted from the array of nano-sized projections and accelerated downstream. There is a ion source electrode downstream of the at least one cathode, and the at least one cathode and the ion source electrode have the same voltage applied such that the electrons enter the space encompassed by the ion source electrode, some of the electrons as they travel within the ion source electrode striking an ionizable gas to create ions.

    Abstract translation: 用于粒子加速器的离子源包括至少一个阴极。 所述至少一个阴极具有纳米尺寸突起的阵列和邻近纳米尺寸突起阵列的门阵列。 纳米尺寸突起阵列和栅极阵列具有第一电压差，使得阴极中的电场使电子从纳米尺寸突起阵列发射并加速下游。 在至少一个阴极的下游存在离子源电极，并且至少一个阴极和离子源电极施加相同的电压，使得电子进入由离子源电极包围的空间中，一些电子就像它们 在离子源电极内行进进入可电离气体以产生离子。

    CONDUCTIVE NANOSTRUCTURE, METHOD FOR MOLDING SAME, AND METHOD FOR MANUFACTURING A FIELD EMITTER USING SAME
    30.
    发明申请
    CONDUCTIVE NANOSTRUCTURE, METHOD FOR MOLDING SAME, AND METHOD FOR MANUFACTURING A FIELD EMITTER USING SAME 有权
    导电性纳米结构，其成型方法以及使用其制造场致发射体的方法

    公开(公告)号：US20130134860A1

    公开(公告)日：2013-05-30

    申请号：US13704902

    申请日：2011-02-23

    Applicant: Yong Hyup Kim ,  Wal Jun Kim

    Inventor： Yong Hyup Kim ,  Wal Jun Kim

    IPC: H01J9/02 ,  H01J1/304 ,  B23H9/00

    CPC classification number: H01J9/025 ,  B23H9/00 ,  H01B1/04 ,  H01B1/08 ,  H01J1/304 ,  H01J1/3044 ,  H01J2201/30411 ,  H01J2201/30434 ,  H01J2201/30449 ,  H01J2201/30469

    Abstract: The present invention relates to a conductive nanostructure, a method for molding the same, and a method for manufacturing a field emitter using the same. More particularly, the present invention relates to a field-emitting nanostructure comprising a conductive substrate, a conductive nanostructure arranged on the conductive substrate, and a conductive interfacial compound disposed in the interface between the conductive substrate and the conductive nanostructure, as well as to a method for molding the same, and a method for manufacturing a field emitter using the same.

    Abstract translation: 导电纳米结构体及其成型方法技术领域本发明涉及导电性纳米结构体，其成型方法及使用其的场致发射体的制造方法。 更具体地说，本发明涉及一种场致发射纳米结构，其包括导电衬底，布置在导电衬底上的导电纳米结构以及布置在导电衬底和导电纳米结构之间的界面中的导电界面化合物，以及一 其制造方法以及使用该场致发射体的制造方法。

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