公开(公告)号：US20150102432A1

公开(公告)日：2015-04-16

申请号：US14053751

申请日：2013-10-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yuan-Chih Hsieh ,  Li-cheng Chu ,  Hung-Hua Lin ,  Chih-Jen Chan ,  Lan-Lin Chao

IPC分类号： B81C1/00 ,  H01L21/322 ,  B81B7/00 ,  H01L23/26

CPC分类号： B81B7/0038 ,  B81B7/0025 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0315 ,  B81C1/00285 ,  B81C2203/0118 ,  H01L21/3223 ,  H01L23/26 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by depositing a gettering material on a roughened substrate surface, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having residual gases. One or more cavities are formed in the substrate at locations between bonding areas on a top surface of the substrate. Respective cavities have roughened interior surfaces that vary in a plurality of directions. A getter layer is deposited into the one or more cavities. The roughened interior surfaces of the one or more cavities enable the substrate to more effectively absorb the residual gases, thereby increasing the efficiency of the gettering process.

摘要翻译： 本公开涉及一种吸气方法，其通过在粗糙化的基底表面上沉积吸气材料和相关联的装置来提供高效吸气过程。 在一些实施例中，通过将衬底提供到具有残留气体的处理室中来执行该方法。 在衬底的顶部表面上的结合区域之间的位置处形成一个或多个空腔。 相应的空腔具有在多个方向上变化的内表面的粗糙化。 吸气剂层沉积到一个或多个空腔中。 一个或多个空腔的粗糙化的内表面使得基底能够更有效地吸收残余气体，从而提高吸气过程的效率。

公开(公告)号：US08883612B2

公开(公告)日：2014-11-11

申请号：US13229861

申请日：2011-09-12

申请人： Hans-Joachim Schulze ,  Francisco Javier Santos Rodriguez ,  Anton Mauder ,  Johannes Baumgartl ,  Carsten Ahrens

发明人： Hans-Joachim Schulze ,  Francisco Javier Santos Rodriguez ,  Anton Mauder ,  Johannes Baumgartl ,  Carsten Ahrens

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/324 ,  H01L21/265 ,  H01L29/16

CPC分类号： H01L21/3223 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02664 ,  H01L21/0475 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/1608

摘要： A method of manufacturing a semiconductor device includes forming a porous area of a semiconductor body. The semiconductor body includes a porous structure in the porous area. A semiconductor layer is formed on the porous area. Semiconductor regions are formed in the semiconductor layer. Then, the semiconductor layer is separated from the semiconductor body along the porous area, including introducing hydrogen into the porous area by a thermal treatment.

公开(公告)号：US08410573B2

公开(公告)日：2013-04-02

申请号：US12734240

申请日：2008-10-20

申请人： Hiroshi Ohtsuki ,  Mitsutaka Katada ,  Nobuhiko Noto ,  Hiroshi Takeno ,  Kazuhiko Yoshida

发明人： Hiroshi Ohtsuki ,  Mitsutaka Katada ,  Nobuhiko Noto ,  Hiroshi Takeno ,  Kazuhiko Yoshida

IPC分类号： H01L29/06

CPC分类号： H01L29/78609 ,  H01L21/26506 ,  H01L21/3221 ,  H01L21/3223 ,  H01L21/3226 ,  H01L21/76256 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/32 ,  H01L29/7849 ,  H01L29/78603

摘要： In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site.

摘要翻译： 在使用SOI衬底的SOI结构半导体器件中，通过将Ar离子注入作为有源层的硅衬底中形成晶格畸变层。 晶格畸变层能够用作吸杂位点。 调整Ar离子的剂量，使晶格变形层的拉伸应力为11MPa以上且27MPa以下。 因此，晶格畸变层可以防止在作为吸杂位置时发生漏电流。

公开(公告)号：US20100264510A1

公开(公告)日：2010-10-21

申请号：US12734240

申请日：2008-10-20

申请人： Hiroshi Ohtsuki ,  Mitsutaka Katada ,  Nobuhiko Noto ,  Hiroshi Takeno ,  Kazuhiko Yoshida

发明人： Hiroshi Ohtsuki ,  Mitsutaka Katada ,  Nobuhiko Noto ,  Hiroshi Takeno ,  Kazuhiko Yoshida

IPC分类号： H01L29/06 ,  H01L21/306

CPC分类号： H01L29/78609 ,  H01L21/26506 ,  H01L21/3221 ,  H01L21/3223 ,  H01L21/3226 ,  H01L21/76256 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/32 ,  H01L29/7849 ,  H01L29/78603

摘要： In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site.

摘要翻译： 在使用SOI衬底的SOI结构半导体器件中，通过将Ar离子注入作为有源层的硅衬底中形成晶格畸变层。 晶格畸变层能够用作吸杂位点。 调整Ar离子的剂量，使晶格变形层的拉伸应力为11MPa以上且27MPa以下。 因此，晶格畸变层可以防止在作为吸杂位置时发生漏电流。

公开(公告)号：US20090209085A1

公开(公告)日：2009-08-20

申请号：US12308990

申请日：2007-06-08

申请人： Akihiko Tamura ,  Konomu Oki

发明人： Akihiko Tamura ,  Konomu Oki

IPC分类号： H01L21/762

CPC分类号： H01L21/76254 ,  H01L21/02032 ,  H01L21/3223 ,  H01L21/3225

摘要： The present invention provides a method for reusing a delaminated wafer, which is a method for applying reprocessing that is at least polishing to a delaminated wafer 17 byproduced when manufacturing an SOI wafer based on an ion implantation delamination method and thereby again reusing the delaminated wafer 17 as a bond wafer 21 in an SOI wafer manufacturing process, wherein, at least, a CZ wafer 11 used as the bond wafer is a low-defect wafer whose entire surface is formed of an N region, and an RTA treatment is carried out in the reprocessing with respect to the delaminated wafer 17 at a higher temperature than a temperature in formation of a thermal oxide film 12 performed with respect to the bond wafer in the SOI wafer manufacturing process. As a result, there can be provided the method for reusing a delaminated wafer which does not induce a bonding failure or a reduction in quality of an SOI layer even if the delaminated wafer byproduced when the CZ wafer having a large diameter of 200 mm or above is used as the bond wafer to fabricate the SOI wafer based on the ion implantation delamination method is repeatedly reused as the bond wafer.

摘要翻译： 本发明提供了一种重新使用分层晶片的方法，其是通过在基于离子注入分层方法制造SOI晶片时通过产生的至少抛光到再分散晶片17的再处理方法，从而再次使用分层晶片17 作为SOI晶片制造工艺中的接合晶片21，其中，至少用作接合晶片的CZ晶片11是整个表面由N区形成的低缺陷晶片，并且RTA处理在 相对于分解晶片17在相对于SOI晶片制造工艺中的接合晶片执行的热氧化膜12的形成温度以上的温度下的再处理。 其结果是，即使在大直径为200mm以上的CZ晶片发生剥离的晶片时，也可以提供不会引起SOI层的接合不良或质量降低的剥离晶片的再利用方法 用作接合晶片以制造SOI晶圆为基础的离子注入分层方法被反复重复使用作为接合晶片。

公开(公告)号：US20080290425A1

公开(公告)日：2008-11-27

申请号：US12119972

申请日：2008-05-13

申请人： Luis-Felipe Giles ,  Thomas Hoffmann ,  Chris Stapelmann

发明人： Luis-Felipe Giles ,  Thomas Hoffmann ,  Chris Stapelmann

IPC分类号： H01L29/00 ,  H01L21/425 ,  H01L21/336

CPC分类号： H01L21/3223 ,  H01L21/263 ,  H01L21/26506 ,  H01L29/66575 ,  H01L29/78

摘要： In a method for fabricating a semiconductor element in a substrate, first implantation ions are implanted into the substrate, whereby micro-cavities are produced in a first partial region of the substrate. Furthermore, pre-amorphization ions are implanted into the substrate, whereby a second partial region of the substrate is at least partly amorphized, and whereby crystal defects are produced in the substrate. Furthermore, second implantation ions are implanted into the second partial region of the substrate. Furthermore, the substrate is heated, such that at least some of the crystal defects are eliminated using the second implantation ions. Furthermore, dopant atoms are implanted into the second partial region of the substrate, wherein the semiconductor element is formed using the dopant atoms.

摘要翻译： 在衬底中制造半导体元件的方法中，将第一注入离子注入到衬底中，从而在衬底的第一部分区域中产生微腔。 此外，将非晶化离子注入到基板中，由此基板的第二部分区域至少部分非晶化，并且由此在基板中产生晶体缺陷。 此外，第二注入离子注入基片的第二部分区域。 此外，加热衬底，使得使用第二注入离子去除至少一些晶体缺陷。 此外，掺杂剂原子被注入到衬底的第二部分区域中，其中使用掺杂剂原子形成半导体元件。

公开(公告)号：US07417297B2

公开(公告)日：2008-08-26

申请号：US11384887

申请日：2006-03-20

申请人： Brian Murphy ,  Reinhold Wahlich ,  Rüdiger Schmolke ,  Wilfried Von Ammon ,  James Moreland

发明人： Brian Murphy ,  Reinhold Wahlich ,  Rüdiger Schmolke ,  Wilfried Von Ammon ,  James Moreland

IPC分类号： H01L29/06

CPC分类号： H01L21/3223 ,  H01L21/76251

摘要： SOI wafers are manufactured to have very thin device layers of high surface quality. The layer is ≦20 nm in thickness, has an HF density of ≦0.1/cm2, and a surface roughness of 0.2 nm RMS.

摘要翻译： SOI晶片被制造成具有非常薄的高表面质量的器件层。 该层的厚度<20nm，HF密度<= 0.1 / CM <2>，表面粗糙度为0.2nm RMS。

公开(公告)号：US20070075401A1

公开(公告)日：2007-04-05

申请号：US11606479

申请日：2006-11-30

申请人： Leonard Forbes ,  Joseph Geusic

发明人： Leonard Forbes ,  Joseph Geusic

IPC分类号： H01L29/30

CPC分类号： H01L27/105 ,  H01L21/3223 ,  H01L21/324 ,  H01L27/108 ,  H01L29/78 ,  Y10S257/913

摘要： One aspect of this disclosure relates to a memory device, comprising at least one gettering region, a memory array, a plurality of word lines and bit lines, and control circuitry. The gettering region is formed in a semiconductor substrate. The gettering region includes a precise arrangement of precisely-formed voids to getter impurities from a crystalline semiconductor region of the substrate. The memory array is formed in the crystalline semiconductor region, and includes a plurality of memory cells formed in rows and columns, and at least one transistor for each of the plurality of memory cells. Each word line is connected to a row of memory cells, and each bit line is connected to a column of memory cells. The control circuitry includes word line select circuitry and bit line select circuitry to select a number of memory cells for writing and reading operations.

摘要翻译： 本公开的一个方面涉及一种存储器件，其包括至少一个吸杂区域，存储器阵列，多个字线和位线以及控制电路。 吸气区形成在半导体衬底中。 吸气区域包括精确设置的精确形成的空隙以从衬底的结晶半导体区域吸收杂质。 存储器阵列形成在晶体半导体区域中，并且包括以行和列形成的多个存储单元，以及用于多个存储单元中的每一个的至少一个晶体管。 每个字线连接到一行存储器单元，并且每个位线连接到一列存储单元。 控制电路包括字线选择电路和位线选择电路，以选择用于写入和读取操作的多个存储器单元。

公开(公告)号：US06929984B2

公开(公告)日：2005-08-16

申请号：US10623794

申请日：2003-07-21

申请人： Leonard Forbes ,  Joseph E. Geusic

发明人： Leonard Forbes ,  Joseph E. Geusic

IPC分类号： H01L21/322 ,  H01L21/324 ,  H01L29/78 ,  H01L21/335 ,  H01L21/8232

CPC分类号： H01L27/105 ,  H01L21/3223 ,  H01L21/324 ,  H01L27/108 ,  H01L29/78 ,  Y10S257/913

摘要： One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer. In various embodiments, a predetermined arrangement of a plurality of holes is formed in the semiconductor wafer through a surface of the wafer. The wafer is annealed such that the wafer undergoes a surface transformation to transform the arrangement of the plurality of holes into a predetermined arrangement of at least one empty space of a predetermined size within the wafer to form the gettering site. One aspect relates to a semiconductor wafer. In various embodiments, the wafer includes at least one device region, and at least one gettering region located proximate to the at least one device region. The gettering region includes a precisely-determined arrangement of a plurality of precisely-formed voids that are formed within the wafer using a surface transformation process. Other aspects and embodiments are provided herein.

公开(公告)号：US20190139856A1

公开(公告)日：2019-05-09

申请号：US16107470

申请日：2018-08-21

申请人： National Technology & Engineering Solutions of Sandia, LLC ,  University of Virginia Patent Foundation

发明人： Thomas Edwin Beechem, III ,  Khalid Mikhiel Hattar ,  Jon Ihlefeld ,  Edward S. Piekos ,  Douglas L. Medlin ,  Luke Yates ,  Patrick E. Hopkins

IPC分类号： H01L23/373 ,  H01L21/265

CPC分类号： H01L23/373 ,  H01L21/265 ,  H01L21/322 ,  H01L21/3223 ,  H01L23/34

摘要： Ion implantation can be used to define a thermal dissipation path that allows for better thermal isolation between devices in close proximity on a microelectronics chip, thus providing a means for higher device density combined with better performance.