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    Method of manufacturing self aligned electrode with field insulation
    21.
    发明授权
    Method of manufacturing self aligned electrode with field insulation 失效
    制造具有场绝缘的自对准电极的方法

    公开(公告)号：US06987065B2

    公开(公告)日：2006-01-17

    申请号：US10891038

    申请日：2004-07-15

    Applicant: Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Akira Inoue

    Inventor： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Akira Inoue

    IPC: H01L21/311

    CPC classification number: H01L29/78696 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78687 ,  Y10S438/933 ,  Y10S438/938

    Abstract: The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.

    Abstract translation: 本发明提供一种半导体器件，包括：半导体层（3）; 经由栅极绝缘膜（10）形成在所述半导体层（3）上的栅电极（11）; 以及形成在所述半导体层（3），所述栅极绝缘膜（10）和所述栅电极（11）的侧壁的一个或多个的第一绝缘膜（13）。 其中所述第一绝缘膜（13）覆盖所述栅极绝缘膜（10）表面的一部分。 根据半导体装置，可以抑制隔离边缘处的漏电流，从而可以提高可靠性。

    Method for manufacturing SOI LOCOS MOSFET with metal oxide film or impurity-implanted field oxide
    22.
    发明授权
    Method for manufacturing SOI LOCOS MOSFET with metal oxide film or impurity-implanted field oxide 失效
    制造具有金属氧化物膜或杂质注入场氧化物的SOI LOCOS MOSFET的方法

    公开(公告)号：US06977205B2

    公开(公告)日：2005-12-20

    申请号：US10765156

    申请日：2004-01-28

    Applicant: Hirotaka Komatsubara

    Inventor： Hirotaka Komatsubara

    IPC: H01L21/316 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L21/00 ,  H01L21/425 ,  H01L21/84

    CPC classification number: H01L29/78696 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78654

    Abstract: This invention provides a semiconductor device with an element isolation implemented by a method of manufacturing a semiconductor device comprising the steps of: forming a pad oxide film 140 and a nitride film 150 sequentially on a silicon layer 130 in an element region S; forming a metal oxide film 180 for generating a fixed electric charge on the nitride film 150 and on the silicon layer 130 in an element isolation region A; forming a field oxide film 160 in the element isolation region A by implementing an oxidation treatment; and removing the metal oxide film 180 on the nitride film 150, the nitride film 150 and the pad oxide film 140. In the semiconductor device, the threshold voltage of a parasitic transistor is made high and prevented from turning on, and the influence of leak current is reduced and the hump characteristic of element is restrained.

    Abstract translation: 本发明提供了一种半导体器件，其具有通过制造半导体器件的方法实现的元件隔离，包括以下步骤：在元件区域S中的硅层130上依次形成衬垫氧化物膜140和氮化物膜150; 形成金属氧化物膜180，用于在元件隔离区域A中的氮化物膜150和硅层130上产生固定电荷; 通过实施氧化处理在元件隔离区域A中形成场氧化膜160; 并且去除氮化物膜150，氮化物膜150和衬垫氧化膜140上的金属氧化物膜180.在半导体器件中，使寄生晶体管的阈值电压变高并防止导通，并且泄漏的影响 电流减小，元件的隆起特性受到限制。

    Semiconductor device and method of manufacturing same
    26.
    发明申请
    Semiconductor device and method of manufacturing same 有权
    半导体装置及其制造方法

    公开(公告)号：US20040222465A1

    公开(公告)日：2004-11-11

    申请号：US10866701

    申请日：2004-06-15

    Applicant: Renesas Technology Corp.

    Inventor： Takuji Matsumoto ,  Hirokazu Sayama ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Kazunobu Ota

    IPC: H01L029/76 ,  H01L029/94

    CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/4238 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/78615 ,  H01L29/78621 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode (7) of polysilicon is formed partially on the silicon oxide film (6). A portion of the silicon oxide film (6) underlying the gate electrode (7) functions as a gate insulation film. A silicon nitride film (9) is formed on each side surface of the gate electrode (7), with a silicon oxide film (8) therebetween. The silicon oxide film (8) and the silicon nitride film (9) are formed on the silicon oxide film (6). The width (W1) of the silicon oxide film (8) in a direction of the gate length is greater than the thickness (T1) of the silicon oxide film (6).

    Abstract translation: 提供一种半导体器件，其通过降低寄生双极晶体管的增益来实现故障的减小和工作特性变化，及其制造方法。 在硅层（3）的上表面上部分地形成氧化硅膜（6）。 多晶硅的栅电极（7）部分地形成在氧化硅膜（6）上。 栅电极（7）下方的氧化硅膜（6）的一部分用作栅极绝缘膜。 在栅极（7）的每个侧表面上形成氮化硅膜（9），其间具有氧化硅膜（8）。 氧化硅膜（8）和氮化硅膜（9）形成在氧化硅膜（6）上。 氧化硅膜（8）在栅极长度方向上的宽度（W1）大于氧化硅膜（6）的厚度（T1）。

    MOSFET fabrication method
    28.
    发明授权
    MOSFET fabrication method 失效
    MOSFET制造方法

    公开(公告)号：US06727147B2

    公开(公告)日：2004-04-27

    申请号：US10164609

    申请日：2002-06-10

    Applicant: Toshiyuki Nakamura ,  Hideaki Matsuhashi

    Inventor： Toshiyuki Nakamura ,  Hideaki Matsuhashi

    IPC: H01L218236

    CPC classification number: H01L27/1203 ,  H01L21/26506 ,  H01L21/76281 ,  H01L21/84

    Abstract: An FET is fabricated on an SOI substrate by the following processes. Openings are formed in laminated layers of a pad oxide film of about 5-10 nm and an oxidation-resistant nitride film of about 50-150 nm at positions where device isolation regions are to be provided. The substrate is irradiated by an ion implantation apparatus with at least one of Ar ions and Si ions with an implantation energy of 40-50 keV, and a dose of 1×1014 to 5×1015 cm−2. Field oxidation is then conducted to electrically separate adjacent devices. The regions of the substrate where the openings are formed become amorphous when irradiated, and the field oxidation is consequently enhanced. Hence, a thermal oxidation film having sufficient thickness can be obtained even at device isolation regions having isolation widths of 0.2 &mgr;m or less.

    Abstract translation: 通过以下工艺在SOI衬底上制造FET。 在要设置器件隔离区的位置处，在约5-10nm的衬垫氧化膜的层压层和约50-150nm的耐氧化氮化物膜上形成开口。 用离子注入装置用Ar离子和Si离子中的至少一种照射衬底，注入能量为40-50keV，剂量为1×10 14至5×10 15 cm -2。 然后进行场氧化以电隔离相邻的装置。 形成开口部的基板的区域在照射时成为非晶态，因此能够提高场氧化。 因此，即使在隔离宽度为0.2μm以下的器件分离区域，也可以获得具有足够厚度的热氧化膜。

    MOSFET FABRICATION METHOD
    29.
    发明申请
    MOSFET FABRICATION METHOD 失效
    MOSFET制造方法

    公开(公告)号：US20030228735A1

    公开(公告)日：2003-12-11

    申请号：US10164609

    申请日：2002-06-10

    Inventor： Toshiyuki Nakamura ,  Hideaki Matsuhashi

    IPC: H01L021/336

    CPC classification number: H01L27/1203 ,  H01L21/26506 ,  H01L21/76281 ,  H01L21/84

    Abstract: An FET is fabricated on an SOI substrate by the following processes. Openings are formed in laminated layers of a pad oxide film of about 5-10 nm and an oxidation-resistant nitride film of about 50-150 nm at positions where device isolation regions are to be provided. The substrate is irradiated by an ion implantation apparatus with at least one of Ar ions and Si ions with an implantation energy of 40-50 keV, and a dose of 1null1014 to 5null1015 cmnull2. Field oxidation is then conducted to electrically separate adjacent devices. The regions of the substrate where the openings are formed become amorphous when irradiated, and the field oxidation is consequently enhanced. Hence, a thermal oxidation film having sufficient thickness can be obtained even at device isolation regions having isolation widths of 0.2 nullm or less.

    Abstract translation: 通过以下工艺在SOI衬底上制造FET。 在要设置器件隔离区的位置处，在约5-10nm的衬垫氧化膜的层压层和约50-150nm的耐氧化氮化物膜上形成开口。 用离子注入装置用Ar离子和Si离子中的至少一种照射衬底，注入能量为40-50keV，剂量为1×10 14至5×10 15 cm -2。 然后进行场氧化以电隔离相邻的装置。 形成开口部的基板的区域在照射时成为非晶态，因此能够提高场氧化。 因此，即使在隔离宽度为0.2μm以下的器件分离区域，也可以获得具有足够厚度的热氧化膜。

    Methods of fabricating integrated circuit devices including distributed and isolated dummy conductive regions
    30.
    发明授权
    Methods of fabricating integrated circuit devices including distributed and isolated dummy conductive regions 有权
    制造集成电路器件的方法包括分布和隔离的虚拟导电区域

    公开(公告)号：US06656814B2

    公开(公告)日：2003-12-02

    申请号：US09825179

    申请日：2001-04-03

    Applicant: Kwang-dong Yoo ,  Young-wug Kim ,  Seok-kyun Jung

    Inventor： Kwang-dong Yoo ,  Young-wug Kim ,  Seok-kyun Jung

    IPC: H01L2176

    CPC classification number: H01L27/1203 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/76819 ,  H01L21/76885 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

    Abstract: An integrated circuit device is fabricated by forming at least one isolation region in an area of a semiconductor substrate, such as a monolithic semiconductor substrate or a silicon on insulator (SOI) substrate. The at least one isolation region defines at least one active region. A plurality of dummy conductive regions is distributed in the area of the semiconductor substrate, with the dummy conductive regions being constrained to overlie the at least one isolation region. The dummy conductive regions may be formed from a conductive layer that is also used to form, for example, a gate electrode, a capacitor electrode or a wiring pattern. The dummy conductive regions may be formed on an insulation layer, e.g., a gate insulation layer or an interlayer dielectric layer. Preferably, the dummy conductive regions are noncontiguous. In one embodiment, a lattice-shaped isolation region is formed including an array of node regions linked by interconnecting regions and defining an array of dummy active regions. The plurality of dummy conductive regions are formed on the node regions of the lattice-shaped isolation region. In another embodiment, an array of isolation regions is formed, defining a lattice-shaped dummy active region. An array of dummy conductive regions is formed on the array of isolation regions. Related integrated circuit devices are also described.

    Abstract translation: 通过在诸如单片半导体衬底或绝缘体上硅（SOI））衬底的半导体衬底的区域中形成至少一个隔离区域来制造集成电路器件。 所述至少一个隔离区域限定至少一个活性区域。 多个虚设导电区域分布在半导体衬底的区域中，其中虚拟导电区域被限制为覆盖至少一个隔离区域。 虚拟导电区域可以由也用于形成例如栅电极，电容器电极或布线图案的导电层形成。 虚拟导电区域可以形成在绝缘层上，例如栅极绝缘层或层间电介质层。 优选地，虚拟导电区域是不连续的。 在一个实施例中，形成格子状隔离区域，其包括通过互连区域链接并限定虚拟活动区域阵列的节点区域阵列。 多个虚设导电区域形成在格子状隔离区域的节点区域上。 在另一个实施例中，形成隔离区域阵列，限定了格状的虚拟有源区域。 在隔离区域阵列上形成一个虚拟导电区域阵列。 还描述了相关的集成电路器件。

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