公开(公告)号：US4245277A

公开(公告)日：1981-01-13

申请号：US951225

申请日：1978-10-13

Applicant: Cornelis L. M. van Gils ,  Marius H. van der Dussen ,  Pieter Kemkers

Inventor： Cornelis L. M. van Gils ,  Marius H. van der Dussen ,  Pieter Kemkers

IPC: H01G9/12 ,  H01G9/00 ,  B01J17/00

CPC classification number: H01G9/12 ,  Y10T29/417

Abstract: Electrolytic capacitors are provided with a pressure-relief valve which opens if the gas pressure inside the capacitor exceeds a given value to relieve the pressure. In the case of severe electrical overloading, however, the gas-relief passage usually is of insufficient size to prevent excessive pressure build-up, and there is a possibility of explosions. The present invention provides a capacitor in which the pressure-relief valve comprises a venting aperture in a bowl-shaped recess member with the aperture being closed by an elastic member held in compression over the aperture by a thermoplastic strip secured at its ends to the wall of the capacitor housing. The valve is self-sealing for minor pressure increases, but with severe increases a rapid temperature rise of the capacitor roll softens the thermoplastic strip which then allows the elastic member to be blown away so that the aperture becomes directly open to the atmosphere and allows the excessive pressure to be released very rapidly to prevent any possible explosion.

Abstract translation: 电解电容器设有减压阀，如果电容器内部的气体压力超过给定值以释放压力，则其将打开。 然而，在严重的电气超载的情况下，气体释放通道的尺寸通常不足以防止过度的压力积聚，并且存在爆炸的可能性。 本发明提供了一种电容器，其中减压阀包括在碗形凹入部件中的通气孔，孔由弹性构件封闭，该弹性构件通过热塑性带固定在孔的上方，该热塑性带在其端部固定到壁 的电容器外壳。 该阀是自密封的，用于轻微的压力增加，但是随着电容器辊的快速升高使得热塑性带软化，这使得弹性构件被吹走，使得孔径直接向大气敞开，并允许 过高的压力被非常迅速地释放，以防止任何可能的爆炸。

公开(公告)号：US4242791A

公开(公告)日：1981-01-06

申请号：US77699

申请日：1979-09-21

Applicant: Cheng T. Horng ,  Harold V. Lillja ,  David K. Seto

Inventor： Cheng T. Horng ,  Harold V. Lillja ,  David K. Seto

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/266 ,  H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L29/10 ,  B01J17/00

CPC classification number: H01L29/1004 ,  H01L21/033 ,  H01L21/31687 ,  Y10S148/131

Abstract: Disclosed is a method for fabricating very high performance semiconductor devices, particularly bipolar-type transistors having a heavily doped inactive base and a lightly doped narrow active base formed by ion implantation. In order to prevent the high dose boron implantation, for an NPN transistor, from getting into the active base region, a self-aligned mask covering the emitter contact i.e., active base region, is required for inactive base implantation. The self-aligned mask is anodically oxidized aluminum pads. The device wafer metallized with blanket aluminum film is immersed in a dilute H.sub.2 SO.sub.4 solution electrolytic cell which selectively anodizes only the aluminum lands situated over the Si.sub.3 N.sub.4 /SiO.sub.2 defined device contact windows. The aluminum oxide formed by anodization process is porous but may be sealed and densified. The aluminum film that is not anodized is then selectively etched off using either chemical solution or sputter etching. Using the aluminum oxide formed over the contact windows to mask the active base region, a high dose boron implantation is made through the Si.sub.3 N.sub.4 /SiO.sub.2 layers to dope the external base region. After stripping the aluminum oxide from the emitter contact window, the emitter with a desired concentration profile and junction depth is subsequently formed. Formation of the active base is formed by a low dose boron implantation made with its concentration peak below the emitter. A relatively low temperature annealing, as for example, 900.degree. C., is used to fully activate the implanted boron and minimize the redistribution of the active base doping profile. The device thus formed will have a controllable narrow base width and doping profile.

Abstract translation: 公开了一种用于制造非常高性能的半导体器件的方法，特别是具有重掺杂非活性碱和通过离子注入形成的轻掺杂窄活性碱的双极型晶体管。 为了防止对于NPN晶体管的高剂量硼注入进入有源基极区域，需要一个覆盖发射极接触的自对准掩模，即有源基极区域，用于无源基极植入。 自对准掩模是阳极氧化铝垫。 用橡皮布铝膜金属化的器件晶片浸入稀释的H 2 SO 4溶液电解池中，该电解池仅选择性地阳极氧化位于Si 3 N 4 / SiO 2界定的器件接触窗上方的铝焊盘。 通过阳极氧化法形成的氧化铝是多孔的，但可以被密封和致密化。 然后使用化学溶液或溅射蚀刻选择性地蚀刻掉未阳极氧化的铝膜。 使用形成在接触窗口上的氧化铝来掩蔽活性碱性区域，通过Si 3 N 4 / SiO 2层制备高剂量硼注入以掺杂外部碱性区域。 在从发射极接触窗口剥离氧化铝之后，随后形成具有所需浓度分布和结深度的发射极。 活性碱的形成是通过低浓度硼掺杂形成的，其浓度峰值低于发射极。 使用相对低温退火（例如900℃）来完全激活注入的硼并最小化活性碱掺杂分布的再分配。 如此形成的器件将具有可控的窄基极宽度和掺杂分布。

公开(公告)号：US4241493A

公开(公告)日：1980-12-30

申请号：US972246

申请日：1978-12-22

Applicant: William B. Andrulitis ,  Steven G. Miles ,  William T. Kurth

Inventor： William B. Andrulitis ,  Steven G. Miles ,  William T. Kurth

IPC: H01L31/048 ,  B01J17/00

CPC classification number: H01L31/048 ,  B32B17/10018 ,  B32B17/10119 ,  B32B27/20 ,  B32B2367/00 ,  Y02E10/50 ,  Y10T29/49146

Abstract: The solar cell module of this invention is fabricated by placing an array of solar cells in a suitable mold having a bottom surface, an entry port and an exit port. A light transparent superstrate effectively serves as the top for the mold and is placed over the array of solar cells in the mold. The superstrate is spaced from the array such that the superstrate does not come in contact with the top surface of any of the cells or interconnectors of the solar cell array. Clamp means are provided to hold the superstrate in position while encapsulant is pumped into the mold under pressure through the inlet port in an amount sufficient to fill the mold. Thereafter the assembly can be placed in an oven and heated for a time sufficient to cure the encapsulant and bond the materials to each other.

Abstract translation: 通过将太阳能电池阵列放置在具有底面，入口和出口的合适的模具中来制造本发明的太阳能电池组件。 光透明的上层板有效地用作模具的顶部，并放置在模具中的太阳能电池阵列上。 上覆层与阵列间隔开，使得覆层不与太阳能电池阵列的任何电池或互连器的顶表面接触。 提供夹持装置以将覆盖物保持在适当位置，同时将密封剂以足以填充模具的量通过入口在压力下泵入模具中。 此后，组装件可以放置在烘箱中并加热足以固化密封剂并将材料彼此粘合的时间。

公开(公告)号：US4237600A

公开(公告)日：1980-12-09

申请号：US961471

申请日：1978-11-16

Applicant: Arye Rosen ,  Anna M. Gombar ,  Edward Mykietyn

Inventor： Arye Rosen ,  Anna M. Gombar ,  Edward Mykietyn

IPC: H01L21/329 ,  H01L23/482 ,  H01L25/07 ,  B01J17/00

CPC classification number: H01L29/6609 ,  H01L23/482 ,  H01L25/074 ,  H01L2924/0002 ,  Y10S148/028

Abstract: A semiconductor wafer is appropriately doped to create a P-N or P-I-N junction, and metallized on both its planar surfaces with electrode material. The wafer is then bonded to a second similarly processed wafer. Without damaging the semiconductor material, the stacked wafer is processed so as to delineate a plurality of diodes on each side of the center metallization, such that the diodes on each side are registered with each other. The center metallization is then cut so as to yield a plurality of stacked semiconductor diodes.

Abstract translation: 半导体晶片被适当地掺杂以产生P-N或P-I-N结，并在其平面上用电极材料进行金属化。 然后将晶片结合到第二类似处理的晶片。 在不破坏半导体材料的情况下，处理堆叠的晶片以便描绘中心金属化的每一侧上的多个二极管，使得每侧的二极管彼此对准。 然后中心金属化被切割以产生多个堆叠的半导体二极管。

公开(公告)号：US4231149A

公开(公告)日：1980-11-04

申请号：US950191

申请日：1978-10-10

Applicant: Richard A. Chapman ,  Dennis D. Buss ,  Michael A. Kinch

Inventor： Richard A. Chapman ,  Dennis D. Buss ,  Michael A. Kinch

IPC: H01L27/148 ,  B01J17/00

CPC classification number: H01L27/14875 ,  H01L27/14696

Abstract: A monolithic charge-coupled infrared imaging device (CCIRID) is fabricated on N-type HgCdTe. A native oxide layer on the semiconductor is used, in combination with ZnS to provide first level insulation. An opaque field plate over first level insulation is provided for signal channel definition. Second level insulation (ZnS) is substantially thicker than the first level, and is provided with a stepped or sloped geometry under the first level gates. Input and output diodes are provided with MIS guard rings to increase breakdown voltages.

Abstract translation: 在N型HgCdTe上制作了单片电荷耦合红外成像器件（CCIRID）。 与ZnS组合使用半导体上的自然氧化物层以提供一级绝缘。 提供了超过一级绝缘的不透明场板，用于信号通道定义。 第二级绝缘（ZnS）基本上比第一级更厚，并且在第一级门下方设置阶梯式或倾斜几何形状。 输入和输出二极管配有MIS保护环以增加击穿电压。

公开(公告)号：US4227291A

公开(公告)日：1980-10-14

申请号：US918034

申请日：1978-06-22

Applicant: John C. Schumacher

Inventor： John C. Schumacher

IPC: C30B7/12 ,  H01L21/208 ,  H01L31/18 ,  B01J17/00

CPC classification number: C30B7/12 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02628 ,  H01L31/18 ,  H01L31/1804 ,  H01L31/1808 ,  H01L31/1876 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S438/907

Abstract: An energy efficient process is disclosed for the continuous production of semiconductor matrices formed from depositing doped silicon or germanium films on metallic sheet substrates. The energy released from such deposition can then be used to regenerate the anode material used in the deposition.

Abstract translation: 公开了一种节能方法，用于连续生产通过在金属片基底上沉积掺杂的硅或锗膜形成的半导体矩阵。 然后可以使用从这种沉积释放的能量来再生用于沉积中的阳极材料。

公开(公告)号：US4226017A

公开(公告)日：1980-10-07

申请号：US905978

申请日：1978-05-15

Applicant: Joseph Lindmayer

Inventor： Joseph Lindmayer

IPC: H01L21/225 ,  H01L31/068 ,  H01L31/18 ,  B01J17/00

CPC classification number: H01L21/2254 ,  H01L31/068 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S148/033

Abstract: A method for use in making semiconductor type electrical devices such as solar cells. In the method, a wafer of semiconductor material having two major surfaces is provided, the wafer being doped with an impurity of one conductivity type. A layer of a metal-containing compositions such as aluminum, is placed on one of the major surfaces of the wafer, and the wafer is then heated in the presence of an impurity of the opposite conductivity type to a temperature such that a high-low junction is formed by the metal at one major surface while the impurity of the opposite conductivity type diffuses or penetrates the other major surface to form a p-n junction thereat.

Abstract translation: 一种用于制造诸如太阳能电池的半导体型电气装置的方法。 在该方法中，提供具有两个主表面的半导体材料晶片，该晶片掺杂有一种导电类型的杂质。 将一层含金属的组合物如铝放置在晶片的一个主表面上，然后在相反导电类型的杂质存在下将晶片加热至使得高 - 低 接头由一个主表面上的金属形成，而相反导电类型的杂质扩散或穿透另一个主表面以在其上形成pn结。

公开(公告)号：US4222165A

公开(公告)日：1980-09-16

申请号：US945453

申请日：1978-09-25

Applicant: John M. Hartman ,  George S. Leach

Inventor： John M. Hartman ,  George S. Leach

IPC: H01L21/321 ,  H01L21/3215 ,  H01L21/339 ,  H01L29/49 ,  B01J17/00

CPC classification number: H01L29/66954 ,  H01L21/32105 ,  H01L21/32155 ,  H01L29/4983

Abstract: This invention provides the structure for a two-phase charge coupled storage device. Alternate regions of thicker and thinner silicon dioxide are grown upon a silicon substrate. These silicon dioxide regions are covered with a layer of deposited, undoped polysilicon. A layer of silicon dioxide is grown over the polysilicon. Ion implantation is applied to cause isolated regions of conductivity in the polysilicon. Then contact windows are cut in the upper most layer of silicon dioxide exposing the polysilicon therethrough and a metal coating is deposited in the contact windows. Two-phase signals are applied to the resulting electrodes to advance charges at the surface of the silicon substrate.

Abstract translation: 本发明提供了两相电荷耦合存储装置的结构。 较厚和较薄的二氧化硅的替代区域生长在硅衬底上。 这些二氧化硅区域被一层沉积的未掺杂的多晶硅覆盖。 在多晶硅上生长一层二氧化硅。 应用离子注入来引起多晶硅中的隔离导电性区域。 然后，将接触窗口切割成暴露多晶硅的最上层的二氧化硅，并且在接触窗中沉积金属涂层。 对所得电极施加两相信号，以在硅衬底的表面上推进电荷。

公开(公告)号：US4221044A

公开(公告)日：1980-09-09

申请号：US913182

申请日：1978-06-06

Applicant: Gordon C. Godejahn, Jr. ,  Gary L. Heimbigner

Inventor： Gordon C. Godejahn, Jr. ,  Gary L. Heimbigner

IPC: H01L27/11 ,  H01L21/033 ,  H01L21/28 ,  H01L21/32 ,  H01L21/321 ,  H01L21/762 ,  H01L21/8244 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  B01J17/00

CPC classification number: H01L21/033 ,  H01L21/28 ,  H01L21/32 ,  H01L21/321 ,  H01L21/76202 ,  Y10S148/117 ,  Y10S148/141

Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of only desired portions of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliabilty. The process allows the simultaneous doping of two or more regions resulting in uniformity of device characteristics.

Abstract translation: 用于制造VLSI（超大规模集成电路）电路的方法采用用于FET器件的自对准栅极和触点的技术，以及衬底中的扩散导线和位于衬底上形成的隔离场氧化物上的多晶硅导电线的技术。 掩模对准公差增加并呈现非关键性。 在具有不同蚀刻特性的连续层中使用材料允许仅对所述结构的所需部分进行选择性氧化，而不需要通过间歇拆除工艺再次掩蔽并从所需位置去除所选择的材料而不使用掩模。 导致VLSI电路具有增加的密度和可靠性。 该方法允许同时掺杂两个或更多个区域，导致器件特性的均匀性。

公开(公告)号：US4219925A

公开(公告)日：1980-09-02

申请号：US939141

申请日：1978-09-01

Applicant: Richard H. Heeren

Inventor： Richard H. Heeren

IPC: H01L21/033 ,  H01L29/41 ,  H01L29/78 ,  B01J17/00

CPC classification number: H01L21/033 ,  H01L29/78 ,  Y10S148/053 ,  Y10S148/114 ,  Y10S148/141

Abstract: A silicon body (10) of a first conductivity type is covered with a sandwich of silicon dioxide (12), polycrystalline silicon (14) and silicon nitride (16). Source, drain, and interconnect work sites of the body are exposed by a first photoshaping operation. The work sites are doped forming regions (21, 22, 23) of a second conductivity type. Silicon dioxide (24, 26, 28) is grown over the work sites. A second photoshaping operation provides an opening 36. The walls of the opening 36 on two opposite sides comprise sides of the sandwich layer as established by the first photoshaping operation and the two remaining walls comprise sides of the silicon dioxide as established by the second photoshaping operation. Silicon nitride (44) is next deposited over the entire wafer (15) which is then photoshaped to define the field regions (46, 48). The etching process is continued to remove part of the silicon body as well as the sides of those exposed regions. Thereafter, silicon dioxide (47, 49) is grown in the field regions. The remaining silicon nitride layer is removed to reveal the underlying conductive polycrystalline silicon (14) at the gate region, the walls of the contact opening 36 and the interconnect region 23. A conductive material (51, 50) is deposited over the wafer (15) and then photoshaped to provide the desired pattern of ohmic interconnections.

Abstract translation: 第一导电类型的硅体（10）用二氧化硅（12），多晶硅（14）和氮化硅（16）的夹层覆盖。 身体的源，漏和互连工作地点由第一次成像操作暴露。 工作点是第二导电类型的掺杂形成区域（21,22,23）。 二氧化硅（24,26,28）在工作现场生长。 第二次成像操作提供开口36.两个相对侧上的开口36的壁包括通过第一次成形操作建立的夹层的侧面，并且两个剩余的壁包括由第二次成形操作建立的二氧化硅的侧面 。 接着将氮化硅（44）沉积在整个晶片（15）上，然后将其光成型以限定场区（46,48）。 继续蚀刻处理以除去部分硅体以及这些暴露区域的侧面。 此后，在场区域中生长二氧化硅（47,49）。 去除剩余的氮化硅层以在栅极区域，接触开口36的壁和互连区域23处露出下面的导电多晶硅（14）。导电材料（51,50）沉积在晶片（15）上 ），然后进行成像以提供所需的欧姆互连图案。