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    Narrow band-gap semiconductor CCD imaging device and method of fabrication
    2.
    发明授权
    Narrow band-gap semiconductor CCD imaging device and method of fabrication 失效
    窄带隙半导体CCD成像装置及其制造方法

    公开(公告)号：US4231149A

    公开(公告)日：1980-11-04

    申请号：US950191

    申请日：1978-10-10

    申请人： Richard A. Chapman ,  Dennis D. Buss ,  Michael A. Kinch

    发明人： Richard A. Chapman ,  Dennis D. Buss ,  Michael A. Kinch

    IPC分类号： H01L27/148 ,  B01J17/00

    CPC分类号： H01L27/14875 ,  H01L27/14696

    摘要： A monolithic charge-coupled infrared imaging device (CCIRID) is fabricated on N-type HgCdTe. A native oxide layer on the semiconductor is used, in combination with ZnS to provide first level insulation. An opaque field plate over first level insulation is provided for signal channel definition. Second level insulation (ZnS) is substantially thicker than the first level, and is provided with a stepped or sloped geometry under the first level gates. Input and output diodes are provided with MIS guard rings to increase breakdown voltages.

    摘要翻译： 在N型HgCdTe上制作了单片电荷耦合红外成像器件（CCIRID）。 与ZnS组合使用半导体上的自然氧化物层以提供一级绝缘。 提供了超过一级绝缘的不透明场板，用于信号通道定义。 第二级绝缘（ZnS）基本上比第一级更厚，并且在第一级门下方设置阶梯式或倾斜几何形状。 输入和输出二极管配有MIS保护环以增加击穿电压。

    Infrared charge transfer device (CTD) system
    3.
    发明授权
    Infrared charge transfer device (CTD) system 失效
    红外电荷转移装置（CTD）系统

    公开(公告)号：US4360732A

    公开(公告)日：1982-11-23

    申请号：US159990

    申请日：1980-06-16

    申请人： Richard A. Chapman ,  Adam J. Lewis, Jr. ,  Jaroslav Hynecek ,  Michael A. Kinch

    发明人： Richard A. Chapman ,  Adam J. Lewis, Jr. ,  Jaroslav Hynecek ,  Michael A. Kinch

    IPC分类号： H01L27/148 ,  H01J31/49

    CPC分类号： H01L27/14875

    摘要： An infrared charge transfer device (CTD) imaging system is disclosed which includes an optic system for focusing infrared energy emanating from a scene, a detector matrix for receiving the focused infrared energy and converting it to electrical signals representative of the intensity of the infrared energy, and a video processor for processing the electrical signals into video signals. The detector matrix of the system is a plurality of IR detector cells arranged in rows and columns. Each detector cell includes a substrate of semiconductor material, an integrating electrode, a drain electrode, a transfer electrode and insulating layers. The integrating electrode is centrally disposed with respect to the drain and transfer electrodes with the integrating electrode in a spaced relationship with the drain electrode. The integrating and drain electrodes form first level MIS electrodes on the semiconductor substrate. The transfer gate forms a second level MIS electrode as to the semiconductor substrate and overlaps the space between the integrating and drain electrodes. In a second MIS embodiment the drain electrode is replaced by a diode formed in the semiconductor substrate. In both embodiments, the integrating electrodes are connected together in columns and the transfer electrodes are connected together in rows. In operation, the integrating electrode and the drain are on while a row of transfer electrodes are turned on and then off transferring the charge from wells under the integrating electrode to the drain well. The column voltages are sampled before and after the turn-on and turn-off of the integrating well the voltage difference on the column lines is proportional to the charge transferred and is used to indicate the intensity of the impinging infrared image. Charge collected by the drain is either injected to the substrate in the first embodiment or drained out the contact to the junction diode in the second embodiment.

    摘要翻译： 公开了一种红外电荷转移装置（CTD）成像系统，其包括用于聚焦从场景发出的红外能量的光学系统，用于接收聚焦红外能量并将其转换成代表红外能量强度的电信号的检测器矩阵， 以及用于将电信号处理成视频信号的视频处理器。 系统的检测器矩阵是以行和列排列的多个IR检测器单元。 每个检测器单元包括半导体材料的衬底，积分电极，漏电极，转移电极和绝缘层。 积分电极相对于漏极和转移电极居中设置，积分电极与漏极间隔开。 积分和漏电极在半导体衬底上形成第一级MIS电极。 传输栅极形成关于半导体衬底的第二级MIS电极并且与积分和漏极之间的空间重叠。 在第二MIS实施例中，漏电极由形成在半导体衬底中的二极管代替。 在两个实施例中，积分电极以列连接在一起，并且传输电极以行连接在一起。 在工作中，在一排传输电极导通的同时，积分电极和漏极导通，然后将集电极下的电荷转移到排水井。 在积分阱的导通和关断之前和之后对列电压进行采样，列线上的电压差与传送的电荷成比例，并用于指示入射红外图像的强度。 在第二实施例中，由漏极收集的电荷在第一实施例中被注入到衬底中，或者在与第二实施例中的结二极管的接触中被排出。

    Infrared charge injection device imaging system
    4.
    发明授权
    Infrared charge injection device imaging system 失效
    红外电荷注射装置成像系统

    公开(公告)号：US4327291A

    公开(公告)日：1982-04-27

    申请号：US159991

    申请日：1980-06-16

    申请人： Richard A. Chapman ,  Michael A. Kinch ,  Jaroslav Hynecek

    发明人： Richard A. Chapman ,  Michael A. Kinch ,  Jaroslav Hynecek

    IPC分类号： H01L27/146 ,  H01L27/148 ,  H04N5/33 ,  H01J31/49

    CPC分类号： H01L27/14875 ,  H04N5/33

    摘要： An infrared charge transfer device (CTD) imager system is disclosed which includes an optic system, a charge transfer device detector matrix and a signal processor. The optic system focuses infrared energy from a scene onto the detector matrix. The detector matrix produces electrical signals representative of the impinging energy and the signal processor processes the electrical signals into video signals. The CTD detector matrix comprises a plurality of charge injection devices (CID). Each CID has an IR sensitive area, and two metal/insulator/semiconductor gate electrodes surrounded by a field plate. One, a column gate electrode, is centrally located within the IR sensitive area and the other, a row gate electrode, surrounds the column gate electrode. In one embodiment, the field plate and column gate electrode are in a spaced but overlapping relationship with minimum overlap, and the row gate electrode is in a spaced relationship to the field plate and column gate electrode whereby the electric field generated between the edges (corners in particular) of the field plate and column and row gate electrodes is substantially reduced. The column electrode is formed as an integral part of the column read line metallization. In a second embodiment, the column gate electrode is formed in a spaced relationship to the field plate and on the same level without overlap. However, the column read line is spaced above the column electrode and electrically connected through a via. The electric fields at the edges and corners are substantially reduced in this second embodiment.

    摘要翻译： 公开了一种红外电荷转移装置（CTD）成像系统，其包括光学系统，电荷转移装置检测器矩阵和信号处理器。 光学系统将来自场景的红外能量聚焦到检测器矩阵上。 检测器矩阵产生代表入射能量的电信号，信号处理器将电信号处理成视频信号。 CTD检测器矩阵包括多个电荷注入装置（CID）。 每个CID具有IR敏感区域，以及被场板包围的两个金属/绝缘体/半导体栅电极。 一个是列栅电极，位于红外敏感区域的中央，另一个是行栅电极，围绕列栅电极。 在一个实施例中，场板和列栅电极与最小重叠处于间隔但重叠的关系，并且行栅电极与场板和列栅极电极间隔开，由此在边缘（角部 特别地）场板和列栅极电极的电流明显减小。 列电极形成为列读取线金属化的整体部分。 在第二实施例中，列栅极电极以与场板间隔开的关系形成，并且在相同的水平上形成，而不重叠。 然而，列读取线在列电极之间间隔开并且通过通孔电连接。 在该第二实施例中，边缘和角部处的电场大大减小。

    Using a change in doping of poly gate to permit placing both high voltage and low voltage transistors on the same chip
    5.
    发明授权
    Using a change in doping of poly gate to permit placing both high voltage and low voltage transistors on the same chip 失效
    使用多晶硅掺杂的改变，以允许将高压和低压晶体管放置在同一芯片上

    公开(公告)号：US06348719B1

    公开(公告)日：2002-02-19

    申请号：US08698251

    申请日：1996-08-14

    申请人： Richard A. Chapman

    发明人： Richard A. Chapman

    IPC分类号： H01L2976

    CPC分类号： H01L29/4916 ,  H01L27/088 ,  H01L27/0922

    摘要： A semiconductor device having high and low voltage transistors on the same chip. High voltage NMOS transistor 76 comprises a polysilicon gate 40 doped at first dopant level. Low voltage NMOS transistor comprises a polysilicon gate 44 doped at a second dopant level. The second dopant level is higher than the first. High voltage PMOS transistor 84 comprises a polysilicon gate 48 doped at a third dopant level. Low voltage PMOS transistor comprises a polysilicon gate 52 doped at a fourth dopant level. The fourth dopant level is higher than the third.

    摘要翻译： 在同一芯片上具有高低压晶体管的半导体器件。 高电压NMOS晶体管76包括在第一掺杂剂级掺杂的多晶硅栅极40。 低电压NMOS晶体管包括以第二掺杂剂水平掺杂的多晶硅栅极44。 第二掺杂剂水平高于第一掺杂剂水平。 高电压PMOS晶体管84包括以第三掺杂剂水平掺杂的多晶硅栅极48。 低电压PMOS晶体管包括以第四掺杂剂水平掺杂的多晶硅栅极52。 第四种掺杂剂水平高于第三种。

    Integrated circuit isolation process
    7.
    发明授权
    Integrated circuit isolation process 失效
    集成电路隔离过程

    公开(公告)号：US4842675A

    公开(公告)日：1989-06-27

    申请号：US882732

    申请日：1986-07-07

    申请人： Richard A. Chapman ,  Clarence W. Teng

    发明人： Richard A. Chapman ,  Clarence W. Teng

    IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76229 ,  H01L21/76235 ,  Y10S148/05

    摘要： A multiple recess isolation technology avoids stress induced defects while providing a substantially planar surface. A silicon substrate (10) is patterned and etched, creating active moat regions (18) and recesses (20a-b and 21a-b). The recesses are filled with oxide by growing a field oxide (40) in wide recessed regions (21) using a LOCOS process, while depositing a planarization field oxide (44) in narrow recessed regions (20). After etching the structure to obtain a planar surface, standard procedures are used to fabricate the active devices. The process uses a single photolithographic masking step and results in only a very small loss of the width electrically active regions.

    摘要翻译： 多凹陷隔离技术避免了应力诱发的缺陷，同时提供了基本平坦的表面。 对硅衬底（10）进行构图和蚀刻，形成活动的护套区域（18）和凹槽（20a-b和21a-b）。 通过使用LOCOS工艺在宽的凹陷区域（21）中生长场氧化物（40），同时在窄的凹陷区域（20）中沉积平坦化场氧化物（44）来使凹陷填充氧化物。 在蚀刻结构以获得平坦表面之后，使用标准程序来制造有源器件。 该过程使用单个光刻掩模步骤，并且导致宽度电活性区域的非常小的损失。

    Unipolar voltage non-volatile JRAM cell
    8.
    发明授权
    Unipolar voltage non-volatile JRAM cell 失效
    单极性电压非易失性JRAM单元

    公开(公告)号：US4435785A

    公开(公告)日：1984-03-06

    申请号：US269201

    申请日：1981-06-02

    申请人： Richard A. Chapman

    发明人： Richard A. Chapman

    IPC分类号： G11C11/39 ,  G11C16/04 ,  H01L27/07 ,  H01L27/085 ,  H01L29/808 ,  G11C11/24 ,  H01L29/80

    CPC分类号： G11C16/0466 ,  G11C11/39 ,  H01L27/0733 ,  H01L27/085 ,  H01L29/808

    摘要： A non-volatile JRAM cell is constructed to require only positive voltage for programming and erasing of data in the cell. The "well" region of the cell JFET device may be implanted with an impurity concentration that will permit lower breakdown voltage or the non-volatile gate may overlap the JFET gate sufficiently to be able to have the same effect, or some combination of both may be used. This allows the cell to be erased using voltages of one polarity.

    摘要翻译： 构造非易失性JRAM单元仅需要正电压来编程和擦除单元中的数据。 可以注入电池JFET器件的“阱”区域，其杂质浓度将允许更低的击穿电压，或者非易失性栅极可以充分地与JFET栅极重叠以能够具有相同的效果，或两者的某种组合 使用。 这允许使用一个极性的电压擦除电池。