公开(公告)号：US09774316B2

公开(公告)日：2017-09-26

申请号：US15056144

申请日：2016-02-29

Applicant: Altera Corporation

Inventor： Nelson Gaspard ,  Yanzhong Xu

IPC: H03K3/03 ,  H03K3/66 ,  H03K3/013 ,  G11C11/419 ,  H03B5/12 ,  H03L7/085

CPC classification number: H03K3/66 ,  G11C11/419 ,  H03B5/12 ,  H03K3/013 ,  H03K3/03 ,  H03K3/0315 ,  H03K5/1252 ,  H03L7/085

Abstract: A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.

公开(公告)号：US20170250681A1

公开(公告)日：2017-08-31

申请号：US15056144

申请日：2016-02-29

Applicant: Altera Corporation

Inventor： Nelson Gaspard ,  Yanzhong Xu

IPC: H03K3/66 ,  H03K3/013 ,  H03K3/03

CPC classification number: H03K3/66 ,  G11C11/419 ,  H03B5/12 ,  H03K3/013 ,  H03K3/03 ,  H03K3/0315 ,  H03K5/1252 ,  H03L7/085

Abstract: A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.

公开(公告)号：US5942858A

公开(公告)日：1999-08-24

申请号：US581621

申请日：1996-04-08

Applicant: Vladimir Sokolov

Inventor： Vladimir Sokolov

IPC: H02M3/156 ,  G10K9/12 ,  H02M3/155 ,  H03K3/66 ,  H05B33/08 ,  H05B39/04 ,  H05B39/00 ,  H05B39/09

CPC classification number: H05B39/044 ,  H02M3/155 ,  H05B39/047 ,  Y02B20/144 ,  Y02B20/146

Abstract: An apparatus supplies an ohmic, inductive or capacitive load with needle pulse trains in which each individual pulse has a duration of less than 1 millisecond. Due to pulse amplitudes which are by far higher in relation to the nominal voltage of the load, considerable increases in efficiency can be achieved, however, without damaging the load or impairing its useful life. The needle pulses are of constant amplitude and the same polarity. The ratio between pulse voltage and nominal voltage is always higher than 1.7.

Abstract translation: PCT No.PCT / EP94 / 02375 Sec。 371日期：1996年4月8日 102（e）日期1996年4月8日PCT提交1994年7月19日PCT公布。 第WO95 / 03681号公报 日期1995年2月2日一个装置用针脉冲串提供欧姆，电感或电容负载，其中每个脉冲具有小于1毫秒的持续时间。 由于相对于负载的额定电压高得多的脉冲幅度，可以在不损害负载或损害其使用寿命的情况下实现效率的显着提高。 针状脉冲具有恒定幅度和相同的极性。 脉冲电压与额定电压之比始终高于1.7。

公开(公告)号：US3604903A

公开(公告)日：1971-09-14

申请号：US3604903D

申请日：1968-10-23

Applicant: RAMSEY ENG CO

Inventor： HILL JOHN L ,  HOWES NEIL B

IPC: G05D11/13 ,  H03K3/66 ,  H03K21/36

CPC classification number: G05D11/134 ,  H03K3/66

Abstract: An electronic system produces a train of electrical pulses or signals for controlling the dispensing of materials in different amounts or proportions, such as desired in the automatic batching of concrete. By control settings preset on a main electronic decimal counter, a prescribed number of pulses is delivered by the system to a mechanical analog device which in turn controls the material-dispensing mechanism. Additional presettable electronic counters are combined with the main decimal counter to achieve any number of batch formulations proportioned on the basis of arithmetic ratios established by the control settings selected on the counters.

公开(公告)号：US3437911A

公开(公告)日：1969-04-08

申请号：US3437911D

申请日：1966-04-25

Applicant: GEN ELECTRIC

Inventor： GUTZWILLER FRANK W

IPC: H03K3/351 ,  G05F1/445 ,  G05F1/455 ,  H02M1/08 ,  H02P27/02 ,  H03K3/352 ,  H03K3/64 ,  H03K3/66 ,  G05F1/40 ,  G05F1/52 ,  H02M3/08

CPC classification number: H02P27/026 ,  G05F1/445 ,  H02M1/081

公开(公告)号：US10158349B2

公开(公告)日：2018-12-18

申请号：US15466913

申请日：2017-03-23

Applicant: Infineon Technologies AG

Inventor： Walter Kargl ,  Helmut Koroschetz

IPC: H03K3/037 ,  H03K3/66

Abstract: According to one embodiment, an electronic circuit is described comprising an output circuit configured to output data elements, an input circuit configured to receive the data elements from the output circuit wherein the input circuit is clocked by a clock signal and receives the data elements in accordance with its clocking, a signaling circuit configured to, when the output circuit switches from the output of one data element to the output of a following data element, signal to interrupt the clocking of the input circuit and a controller configured to interrupt the clocking of the input circuit in response to the signaling.

公开(公告)号：US20180091122A1

公开(公告)日：2018-03-29

申请号：US15584448

申请日：2017-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Won SHIM ,  Dong-Uk PARK ,  Phil-Jae JEON ,  Sang-Woo PAE ,  Da AHN

IPC: H03K3/66 ,  H03K19/00 ,  H03K5/19

CPC classification number: H03K3/66 ,  G06F1/04 ,  H03K5/135 ,  H03K5/19 ,  H03K19/0002

Abstract: A clock switch device includes a control circuit and a tri-state buffer. The control circuit deactivates an output enable signal when a frequency of a clock signal varies and activates the output enable signal when the frequency of the clock signal is maintained without change. The tri-state buffer maintains an output electrode at a high impedance state when the output enable signal is deactivated and buffers the clock signal and outputs the buffered clock signal through the output electrode as an output clock signal when the output enable signal is activated.

公开(公告)号：US09735759B1

公开(公告)日：2017-08-15

申请号：US15095644

申请日：2016-04-11

Applicant: MOTOROLA SOLUTIONS, INC.

Inventor： Edward A. Diaz ,  Johnny R. Ferreira ,  Ricardo Franco ,  Charles R. Ruelke ,  Richard S. Young

IPC: H03K3/00 ,  H03K3/013 ,  H03K3/66 ,  H03K5/1534

CPC classification number: H03K3/013 ,  H03K3/66 ,  H03K5/1534 ,  H03K19/00346 ,  H03M1/0818 ,  H03M1/0872 ,  H03M1/12

Abstract: A method and apparatus for mitigating electromagnetic noise in an electronic device. The method includes generating a trigger clock signal at a first frequency, and generating a second clock signal at a second frequency. The second frequency is higher than the first frequency. The method also includes receiving an input signal with a converter circuit, detecting an event based on the trigger clock signal, and predicting a time for a conversion of the input signal based on the detected event. The method further includes blanking the second clock signal for a predetermined period based on the predicted time for a conversion.

公开(公告)号：US20170194945A1

公开(公告)日：2017-07-06

申请号：US15464600

申请日：2017-03-21

Applicant: MARVELL WORLD TRADE LTD.

Inventor： Gideon PAUL

IPC: H03K3/012 ,  H03K3/66 ,  H03K5/24 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/356121 ,  H03K3/35625 ,  H03K3/66 ,  H03K5/24

Abstract: Aspects of the disclosure provide a data storage circuit. The data storage circuit includes a first latch, a second latch, and a clock gating and buffer circuit. The first latch is configured to provide an intermediate output to the second latch in response to a data input when a clock signal is in a first state and to hold the intermediate output when the clock signal is in a second state, and the second latch is configured to provide a data output in response to the intermediate output and the clock signal. The clock gating and buffer circuit is configured to provide the clock signal, and to suppress providing the clock signal to one or both of the first latch and the second latch when the intermediate output stays unchanged.

公开(公告)号：US20170141770A1

公开(公告)日：2017-05-18

申请号：US15072613

申请日：2016-03-17

Applicant: SK hynix Inc.

Inventor： Jae Hoon JUNG

IPC: H03K3/66 ,  G11C7/22

CPC classification number: H03K3/66 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225

Abstract: A signal processing circuit may be provided. The signal processing circuit may include a mask generation circuit configured to output a mask signal in response to an internal control signal and masking information; and a masking circuit configured to mask the internal control signal in response to the mask signal, and output a masked control signal, wherein the mask generation circuit resets the mask signal in response to an internal reset signal, regardless of a pause polarity of the internal control signal.