公开(公告)号：US10217512B1

公开(公告)日：2019-02-26

申请号：US15979897

申请日：2018-05-15

申请人： International Business Machines Corporation

发明人： Effendi Leobandung

IPC分类号： G11C11/54 ,  G06N3/04 ,  H01L27/11521 ,  G11C7/16 ,  G11C16/04 ,  H03M1/66

摘要： A neural network unit cell circuit includes multiple floating gate transistors, each of the floating gate transistors having a first source/drain adapted for connection to a common bit line coupled with the unit cell circuit and having a gate adapted for connection to a corresponding one of a plurality of word lines coupled with the unit cell circuit. The unit cell further includes a resistor network having a plurality of resistors connected in a series ladder arrangement, with each node between adjacent resistors operatively connected to a second source/drain of a corresponding one of the floating gate transistors. The resistor network has a first terminal connected to a first voltage source. A readout transistor in the unit cell has a gate coupled with a second terminal of the resistor network, and has first and second source/drains generating an output voltage of the unit cell.

公开(公告)号：US10127954B2

公开(公告)日：2018-11-13

申请号：US15269418

申请日：2016-09-19

申请人： Ovonyx Memory Technology, LLC

发明人： Russel J. Baker

IPC分类号： G11C5/14 ,  G11C7/22 ,  G11C11/56 ,  G11C7/16 ,  G11C7/06 ,  G11C8/08 ,  G11C13/00 ,  H03M3/00

摘要： A system including a processor and a memory device. The memory device includes a memory array having a plurality of memory elements connected to a bit-line and a quantizing circuit. The quantizing circuit includes a combination circuit configured to combine an analog input signal with an analog feedback signal to produce a delta signal. The quantizing circuit also includes an integrator configured to receive and integrate the delta signal to produce a sigma signal. The quantizing circuit also includes an analog-to-digital converter configured to receive the sigma signal and compare the sigma signal with a reference signal to produce a digital output signal.

公开(公告)号：US10090047B2

公开(公告)日：2018-10-02

申请号：US15346841

申请日：2016-11-09

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kohji Hosokawa ,  Masatoshi Ishii ,  Takeo Yasuda

IPC分类号： G11C7/16 ,  G11C13/00 ,  G11C11/4096

摘要： A memory cell structure includes a synapse memory cell including plural cell components, each of the plural cell components including a unit cell, plural write lines arranged for writing a synapse state to the synapse memory cell, each of the plural write lines being used for writing one of a first set of a predetermined number of states to a corresponding cell component by writing one of a second set of the predetermined number of states to the unit cell included in the corresponding cell component, the first set depending on the second set and a number of the unit cell included in the corresponding cell component, and a read line arranged for reading the synapse state from the synapse memory cell, the read line being used for reading one of the first set of the predetermined number of states from all of the plural cell components simultaneously.

公开(公告)号：US10090030B1

公开(公告)日：2018-10-02

申请号：US15581159

申请日：2017-04-28

申请人： Hewlett Packard Enterprise Development LP

发明人： Ali Shafiee Ardestani ,  Naveen Muralimanohar ,  Brent Buchanan

IPC分类号： G11C7/16 ,  G11C7/22 ,  H03M1/34 ,  H03K21/02 ,  H03M1/66

摘要： Examples disclosed herein relate to a circuit having first and second analog processors and an analog-to-digital converter coupled to the first and second analog processors. The first analog processor provides a first analog signal having a voltage representing a function of a first vector and a second vector. The second analog processor provides a second analog signal having a voltage representing a function of a binary inverse of the first vector and the second vector. The analog-to-digital converter receives the first analog signal and the second analog signal, compares a signal selected from a group consisting of the first analog signal and the second analog signal to a reference voltage and based on the comparison to the reference voltage, determines a digital result representing the function of the first vector and the second vector.

公开(公告)号：US20180190330A1

公开(公告)日：2018-07-05

申请号：US15675152

申请日：2017-08-11

申请人： SK hynix Inc.

发明人： Hyun Ju YOON

IPC分类号： G11C7/04 ,  G11C7/06 ,  G11C7/10 ,  G11C7/16 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4093 ,  G11C5/06 ,  G11C5/04

CPC分类号： G11C7/04 ,  G11C5/04 ,  G11C5/06 ,  G11C7/06 ,  G11C7/10 ,  G11C7/16 ,  G11C11/40626 ,  G11C11/4091 ,  G11C11/4093

摘要： A memory module may be provided. The memory module may include a thermocouple and a temperature sensor. The thermocouple may be coupled to at least one contact point among a plurality of contact points formed on a region, on which a memory device may be configured to be mounted. The temperature sensor may be coupled to the thermocouple, and may be configured to generate temperature information.

公开(公告)号：US20180082747A1

公开(公告)日：2018-03-22

申请号：US15823662

申请日：2017-11-28

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Hikaru TAMURA

IPC分类号： G11C16/10 ,  G11C7/16 ,  G11C7/10 ,  G11C11/40

CPC分类号： G11C16/10 ,  G11C7/1078 ,  G11C7/16 ,  G11C11/40

摘要： Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90. Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.

公开(公告)号：US20180068722A1

公开(公告)日：2018-03-08

申请号：US15801372

申请日：2017-11-02

申请人： Eby Friedman ,  Isaac Richter ,  Xiaochen Guo ,  Mohammad Kazemi ,  Kamil Pas ,  Ravi Patel ,  Engin Ipek ,  Ji Liu

发明人： Eby Friedman ,  Isaac Richter ,  Xiaochen Guo ,  Mohammad Kazemi ,  Kamil Pas ,  Ravi Patel ,  Engin Ipek ,  Ji Liu

IPC分类号： G11C13/00 ,  G11C7/16

CPC分类号： G11C13/004 ,  G11C7/16 ,  G11C13/0002 ,  G11C13/0069

摘要： Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

公开(公告)号：US20170310333A9

公开(公告)日：2017-10-26

申请号：US14798442

申请日：2015-07-13

申请人： Infineon Technologies AG

发明人： Dieter DRAXELMAYR

IPC分类号： H03M1/06 ,  H03M1/10 ,  G11C7/16

CPC分类号： H03M1/0617 ,  G11C7/16 ,  H03M1/1009 ,  H03M1/1052 ,  H03M1/12 ,  H03M1/66

摘要： Methods and devices are provided in which a first parameter partial value (p1) is stored in a first memory (12) and a second parameter partial value (p2) is stored in a second memory (13). A parameter value (p) of a parameter can then be obtained by combining the first parameter partial value (p1) with the second parameter partial value (p2).

公开(公告)号：US09800252B2

公开(公告)日：2017-10-24

申请号：US14798442

申请日：2015-07-13

申请人： Infineon Technologies AG

发明人： Dieter Draxelmayr

IPC分类号： H03M1/06 ,  G11C7/16 ,  H03M1/10

CPC分类号： H03M1/0617 ,  G11C7/16 ,  H03M1/1009 ,  H03M1/1052 ,  H03M1/12 ,  H03M1/66

摘要： Methods and devices are provided in which a first parameter partial value (p1) is stored in a first memory (12) and a second parameter partial value (p2) is stored in a second memory (13). A parameter value (p) of a parameter can then be obtained by combining the first parameter partial value (p1) with the second parameter partial value (p2).

公开(公告)号：US09772779B2

公开(公告)日：2017-09-26

申请号：US15098574

申请日：2016-04-14

申请人： MICRON TECHNOLOGY, INC.

发明人： Luca De Santis ,  Luigi Pilolli

IPC分类号： G11C5/14 ,  G06F3/06 ,  G11C11/4074 ,  G11C16/10 ,  G11C7/16 ,  G11C11/4096 ,  G11C7/10 ,  G06F13/16 ,  G11C16/06 ,  G06F12/0875 ,  G06F12/0893

CPC分类号： G06F3/061 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0875 ,  G06F12/0893 ,  G06F13/1668 ,  G06F2212/2022 ,  G06F2212/452 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/16 ,  G11C11/4074 ,  G11C11/4096 ,  G11C16/06 ,  G11C16/10 ,  G11C2207/2245 ,  Y02D10/13 ,  Y02D10/14

摘要： Methods for operating a distributed controller system in a memory device include receiving a read command, a master controller generating an indication to a data cache controller in response to the read command, and the data cache controller accepting data from a memory array of the memory device in response to the indication.