公开(公告)号：US20240332356A1

公开(公告)日：2024-10-03

申请号：US18193445

申请日：2023-03-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L29/06 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/0673 ,  H01L21/823807 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

摘要： A device includes a stack of first nanostructures, wherein each first nanostructure includes a channel region with a first width; a first gate on the stack of first nanostructures, wherein each first nanostructure is surrounded by the first gate, wherein a distance from a first end of the first gate to an adjacent first nanostructure is a first distance; a stack of second nanostructures, wherein each second nanostructure includes a channel region with a second width greater than the first width; a second gate on the stack of second nanostructures, wherein each second nanostructure is surrounded by the second gate, wherein a second distance from a first end of the second gate to an adjacent second nanostructure is greater than the first distance; and a first isolation structure extending continuously from the first end of the first gate to the first end of the second gate.

公开(公告)号：US20240332301A1

公开(公告)日：2024-10-03

申请号：US18129871

申请日：2023-04-02

申请人： Intel Corporation

发明人： Willy RACHMADY ,  Caleb BARRETT ,  Prashant WADHWA ,  Chun-Kuo HUANG ,  Conor P. PULS ,  Daniel James HARRIS ,  Giorgio MARIOTTINI ,  Patrick MORROW

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

摘要： Integrated circuit structures having sub-fin isolation, and methods of fabricating integrated circuit structures having sub-fin isolation, are described. For example, an integrated circuit structure includes a channel structure, and an oxide sub-fin structure over the channel structure, the oxide sub-fin structure including silicon and oxygen and aluminum.

公开(公告)号：US20240332296A1

公开(公告)日：2024-10-03

申请号：US18193595

申请日：2023-03-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ruilong Xie ,  Julien Frougier ,  Huimei Zhou ,  Alexander Reznicek

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

摘要： A semiconductor device includes a vertical insulator pillar extending from the substrate. A first stack of horizontal sheets of a first channel device is coupled to a lateral first side of the vertical insulator pillar and a second stack of horizontal sheets of a second channel device is coupled to a lateral second side of the vertical insulator pillar, opposite the first stack of horizontal sheets. A first gate stack is wrapped around the first stack of horizontal sheets. A second gate stack is wrapped around the second stack of horizontal sheets. A first gate extension is coupled to a center portion of the first gate stack and extending laterally away from the second gate stack and a second gate extension is coupled to a center portion of the second gate stack and extending laterally away from the first gate stack.

公开(公告)号：US20240332293A1

公开(公告)日：2024-10-03

申请号：US18129066

申请日：2023-03-30

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Albert M. Chu ,  Dureseti Chidambarrao ,  Brent A. Anderson

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L27/092 ,  H01L21/28123 ,  H01L21/76895 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5286 ,  H01L23/535 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

摘要： A gate contact is formed within a gate cut region of a semiconductor structure to facilitate electrical routing. The gate contact includes a bottom portion extending within the gate cut region and adjoining a vertical end portion of a metal gate. A metal layer on the front side of the semiconductor structure includes signal tracks, one or more of which is vertically above the gate cut region. A signal track in the metal layer may be electrically connected to the gate contact. Selected source/drain regions within the semiconductor structure may be electrically connected to a back side power delivery network.

公开(公告)号：US12108595B2

公开(公告)日：2024-10-01

申请号：US17001525

申请日：2020-08-24

申请人： Intel Corporation

发明人： Sumit Ashtekar ,  Rahul Ramaswamy ,  Walid Hafez ,  Hector M. Saavedra Garcia

IPC分类号： H01L21/8238 ,  H01H85/02 ,  H01L29/66 ,  H01L29/78 ,  H10B20/20

CPC分类号： H10B20/20 ,  H01H85/0241 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01H2085/0283

摘要： A device structure includes a first gate on a first fin, a second gate on a second fin, where the second gate is spaced apart from the first gate by a distance. A fuse spans the distance and is in contact with the first gate and the second gate. A first dielectric is between the first fin and the second fin, where the first dielectric is in contact with, and below, the fuse and a second dielectric is between the first gate and the second gate, where the second dielectric is on the fuse.

公开(公告)号：US12107163B2

公开(公告)日：2024-10-01

申请号：US17406395

申请日：2021-08-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tsai-Jung Ho ,  Tze-Liang Lee

IPC分类号： H01L21/265 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/7847 ,  H01L29/04 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L21/823814 ,  H01L21/823821

摘要： A semiconductor device structure, along with methods of forming such, are described. In one embodiment, a method for forming a semiconductor device structure is provided. The method includes forming a sacrificial gate structure over a portion of a semiconductor fin, forming a gate spacer on opposing sides of the sacrificial gate structure, forming an amorphized region in the semiconductor fin not covered by the sacrificial gate structure and the gate spacer, wherein the amorphized region has an amorphous-crystalline interface having a first roughness, forming a stressor layer over the amorphized region, wherein the formation of the stressor layer recrystallizes the amorphous-crystalline interface from the first roughness to a second roughness that is less than the first roughness, and subjecting the amorphized region to an annealing process to recrystallize the amorphized region to a crystalline region, and the crystalline region comprising a dislocation.

公开(公告)号：US12107162B2

公开(公告)日：2024-10-01

申请号：US17132293

申请日：2020-12-23

申请人： Winbond Electronics Corp.

发明人： Hung-Yu Wei ,  Pei-Hsiu Peng ,  Kai Jen

IPC分类号： H01L29/78 ,  H01L21/77 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L21/84 ,  H01L27/088

CPC分类号： H01L29/7831 ,  H01L21/77 ,  H01L21/823431 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/41791

摘要： A multi-gate semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate having an active area and an isolation structure adjacent to the active area. The semiconductor structure includes a gate structure formed on the substrate and a gate dielectric layer between the gate structure and the substrate. The gate structure includes a first part above the top surface of the substrate and a second part connected to the first part. The second part of the gate structure is formed in the isolation structure, wherein the isolation structure is in direct contact with the bottom surface and sidewalls of the second part of the gate structure. A method of manufacturing the semiconductor structure includes partially etching the isolation structure to form a trench exposing the top portion of sidewalls of the substrate. The gate dielectric layer and the gate structure extend into the trench.

公开(公告)号：US12107149B2

公开(公告)日：2024-10-01

申请号：US18302474

申请日：2023-04-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Jhe Sie ,  Chen-Huang Huang ,  Shao-Hua Hsu ,  Cheng-Chung Chang ,  Szu-Ping Lee ,  An Chyi Wei ,  Shiang-Bau Wang ,  Chia-Jen Chen

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L21/76832 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

摘要： In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

公开(公告)号：US12107134B2

公开(公告)日：2024-10-01

申请号：US18065442

申请日：2022-12-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Ming Lin ,  Peng-Soon Lim ,  Zi-Wei Fang

IPC分类号： H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/823437 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823821

摘要： A device includes a semiconductor channel region and a gate structure. The semiconductor channel region is on a substrate. The gate structure is over the semiconductor channel region and comprises a gate dielectric layer, a first gate conductor layer, and a second gate conductor layer. The first gate conductor layer is over the gate dielectric layer. The first gate conductor layer includes oxygen. The second gate conductor layer is over the first gate conductor layer.

公开(公告)号：US12107011B2

公开(公告)日：2024-10-01

申请号：US18360332

申请日：2023-07-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chun-Yuan Chen ,  Li-Zhen Yu ,  Huan-Chieh Su ,  Lo-Heng Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC分类号： H01L21/8234 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/823418 ,  H01L21/76224 ,  H01L21/7682 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696 ,  H01L29/6681

摘要： During a front side process of a wafer, a hard mask layer is formed under a metal portion of a semiconductor device, and an epitaxial layer is deposited to form epitaxial portions of the semiconductor device. In a back side process of the wafer to cut the epitaxial layer, the metal portion is covered and protected by the hard mask layer from damages during etching of the epitaxial layer.