公开(公告)号：US20210278611A1

公开(公告)日：2021-09-09

申请号：US16807811

申请日：2020-03-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Asli Sahin ,  Colleen Meagher ,  Thomas Houghton ,  Bo Peng ,  Karen Nummy ,  Javier Ayala ,  Yusheng Bian

IPC: G02B6/42 ,  H01L21/84 ,  H01L21/311

Abstract: One illustrative device disclosed herein includes a V-groove in a base semiconductor layer of a semiconductor-on-insulator (SOI) substrate, wherein the V-groove is adapted to have a fiber optics cable positioned therein, and an optical component positioned above the V-groove. The device also includes a first layer of silicon dioxide positioned above the optical component, a second layer of silicon dioxide positioned on and in contact with the first layer of silicon dioxide and a third layer of silicon dioxide positioned on and in contact with the second layer of silicon dioxide.

公开(公告)号：US11107884B2

公开(公告)日：2021-08-31

申请号：US16538062

申请日：2019-08-12

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  Anthony K. Stamper ,  Laura J. Silverstein ,  Cameron E. Luce

IPC: H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.

公开(公告)号：US20210265342A1

公开(公告)日：2021-08-26

申请号：US16796326

申请日：2020-02-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Wenjun Li ,  Man Gu

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

Abstract: Integrated circuit (IC) structures including buried insulator layer and methods for forming are provided. In a non-limiting example, a IC structure includes: a substrate; a first fin over the substrate; a source region and a drain region in the first fin; a first gate structure and a second gate structure over the first fin, the first and the second gate structures positioned between the source region and the drain region; and a buried insulator layer including a portion disposed under the first fin.

公开(公告)号：US20210249508A1

公开(公告)日：2021-08-12

申请号：US17243832

申请日：2021-04-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jiehui Shu ,  Baofu Zhu ,  Haiting Wang ,  Sipeng Gu

IPC: H01L29/08 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

公开(公告)号：US11087814B2

公开(公告)日：2021-08-10

申请号：US16508940

申请日：2019-07-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Amogh Agrawal ,  Ajey Poovannummoottil Jacob ,  Bipul C. Paul

IPC: G11C11/16

Abstract: The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.

公开(公告)号：US20210242344A1

公开(公告)日：2021-08-05

申请号：US16781236

申请日：2020-02-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Sipeng Gu ,  Jiehui Shu ,  Baofu Zhu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a channel region in a semiconductor body. The gate structure has a first side surface and a second side surface opposite the first side surface. A first source/drain region is positioned adjacent to the first side surface of the gate structure and a second source/drain region is positioned adjacent to the second side surface of the gate structure. The first source/drain region includes a first epitaxial semiconductor layer, and the second source/drain region includes a second epitaxial semiconductor layer. A first top surface of the first epitaxial semiconductor layer is positioned at a first distance from the channel region, a second top surface of the second epitaxial semiconductor layer is positioned at a second distance from the channel region, and the first distance is greater than the second distance.

公开(公告)号：US20210242339A1

公开(公告)日：2021-08-05

申请号：US16776938

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S, Inc.

Inventor： Wenjun Li ,  Man Gu ,  Baofu Zhu

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/8238

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a semiconductor body, a first source/drain region includes an epitaxial semiconductor layer on a first portion of the semiconductor body, and a second source/drain region is positioned in a second portion of the semiconductor body. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure. The first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.

公开(公告)号：US20210242335A1

公开(公告)日：2021-08-05

申请号：US16776930

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Alexander L. Martin ,  Alexander M. Derrickson

IPC: H01L29/735 ,  H01L21/285 ,  H01L29/10 ,  H01L21/308 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L21/266 ,  H01L21/265 ,  H01L29/45 ,  H01L21/3065

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a semiconductor base on a first portion of a raised region of an insulative layer; a first inner emitter/collector (E/C) material on a second portion of the raised region of the insulative layer, wherein the inner E/C material is directly horizontally between the semiconductor base and a sidewall of the raised region; and a first outer E/C material on a first non-raised region of the insulative layer, wherein an upper portion of the first outer E/C material is adjacent the first inner E/C material.

公开(公告)号：US20210242316A1

公开(公告)日：2021-08-05

申请号：US16776711

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Heng Yang ,  David Pritchard ,  Kai Sun ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/417 ,  H01L29/16 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.

公开(公告)号：US20210242306A1

公开(公告)日：2021-08-05

申请号：US16780494

申请日：2020-02-03

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Shiv Kumar MISHRA ,  Baofu ZHU ,  Arkadiusz MALINOWSKI ,  Kaushikee MISHRA

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/74 ,  H01L29/10 ,  H01L21/762 ,  H01L29/66 ,  H01L21/266 ,  H01L21/265

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dual trench isolation structures and methods of manufacture. The structure includes: a doped well region in a substrate; a dual trench isolation region within the doped well region, the dual trench isolation region comprising a first isolation region of a first depth and a second isolation region of a second depth, different than the first depth; and a gate structure on the substrate and extending over a portion of the dual trench isolation region.