公开(公告)号：US20170170300A1

公开(公告)日：2017-06-15

申请号：US14968916

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is conformally formed to cover the sidewalls of the spacers, the exposed portion of the semiconductor fin and the exposed portions of the insulators, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed on the second dielectric layer and between the spacers.

公开(公告)号：US09660052B2

公开(公告)日：2017-05-23

申请号：US14850441

申请日：2015-09-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Tung-Wen Cheng ,  Yi-Jen Chen ,  Yung-Jung Chang

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/36 ,  H01L29/06 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/02 ,  H01L21/265 ,  H01L29/165 ,  H01L29/167

CPC classification number: H01L29/66636 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3086 ,  H01L29/0603 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: Mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers.

公开(公告)号：US20170110579A1

公开(公告)日：2017-04-20

申请号：US14883636

申请日：2015-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

公开(公告)号：US09627537B1

公开(公告)日：2017-04-18

申请号：US14990794

申请日：2016-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L23/535 ,  H01L21/311

CPC classification number: H01L29/785 ,  H01L21/31111 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L2029/7858

Abstract: Provided is a FinFET device including a substrate having at least one fin, first and second gate stacks, first and second strained layers, a shielding layer and first and second connectors. The first and second gate stacks are across the fin. The first and second strained layers are respectively aside the first and second gate stacks. The shielding layer is over the second gate stack, over a top surface and a sidewall of the first gate stack and discontinuous around a top corner of the first gate stack. The first connector is through the shielding layer and is electrically connected to the first stained layer. The second connector is through the shielding layer and is electrically connected to the second stained layer. Besides, the width of the second connector is greater than the width of the first connector.

公开(公告)号：US09627379B1

公开(公告)日：2017-04-18

申请号：US15062219

申请日：2016-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/82 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/0657 ,  H01L29/66545

Abstract: FinFET devices and methods of forming the same are disclosed. One FinFET device includes a substrate with first and second fins in a first region and third and fourth fins in a second region, and first to fourth gates respectively across the first to fourth fins. The first end sidewall of the first gate is faced to the second end sidewall of the second gate, and a first opening is formed between the first and second end sidewalls. The third end sidewall of the third gate is faced to the fourth end sidewall of the fourth gate, and a second opening is formed between the third and fourth end sidewalls. The first and second regions have different pattern densities, and the included angle between the sidewall of the first opening and the substrate is different from the included angle between the sidewall of the second opening and the substrate.

公开(公告)号：US09620417B2

公开(公告)日：2017-04-11

申请号：US14502784

申请日：2014-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Tung-Wen Cheng ,  Che-Cheng Chang ,  Jr-Jung Lin ,  Chih-Han Lin

IPC: H01L21/8234 ,  H01L21/3213 ,  H01J37/32

CPC classification number: H01J37/32449 ,  H01J2237/334 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/67069 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481

Abstract: A method of manufacturing a Fin-FET device includes forming a plurality of fins in a substrate, which the substrate includes a center region and a periphery region surrounding the center region. A gate material layer is deposited over the fins, and the gate material layer is etched with an etching gas to form gates, which the etching gas is supplied at a ratio of a flow rate at the center region to a flow rate at the periphery region in a range from 0.33 to 3.

公开(公告)号：US09570567B1

公开(公告)日：2017-02-14

申请号：US14984514

申请日：2015-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L21/02068 ,  H01L21/30604 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET includes a substrate, a fin structure, a dielectric layer, a metal gate, two spacers, a source and a drain. The fin structure is disposed on the substrate. The dielectric layer is disposed on the fin structure and covers two opposite side surfaces of the fin structure. The dielectric layer includes two first portions protruding from the side surfaces of the fin structure, such that two opposite first recesses are formed in the dielectric layer. The metal gate is disposed on a second portion of the dielectric layer which is sandwiched between the first portions. The spacers are disposed on the first portions of the dielectric layer and protrude from the first portions of the dielectric layer respectively, such that two second recesses are formed in the spacers. The source and drain are respectively disposed in the first recesses and the second recesses on the substrate.

Abstract translation: FinFET包括衬底，鳍结构，电介质层，金属栅极，两个间隔物，源极和漏极。 翅片结构设置在基板上。 电介质层设置在翅片结构上并且覆盖翅片结构的两个相对的侧表面。 电介质层包括从翅片结构的侧表面突出的两个第一部分，使得在电介质层中形成两个相对的第一凹部。 金属栅极设置在夹在第一部分之间的电介质层的第二部分上。 间隔物设置在电介质层的第一部分上，并且从电介质层的第一部分突出，使得在间隔物中形成两个第二凹槽。 源极和漏极分别设置在基板的第一凹部和第二凹部中。

公开(公告)号：US09559165B2

公开(公告)日：2017-01-31

申请号：US14490838

申请日：2014-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Tung-Wen Cheng ,  Chang-Yin Chen ,  Che-Cheng Chang ,  Mu-Tsang Lin

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/092 ,  H01L29/161 ,  H01L21/20 ,  H01L21/302 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165 ,  H01L29/16 ,  H01L29/24 ,  H01L21/3065

CPC classification number: H01L29/0847 ,  H01L21/3065 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/24 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a first gate structure and a second gate structure formed over the substrate. The semiconductor structure further includes first recesses formed in the substrate adjacent to the first gate structure and first strained source and drain structures formed in the first recesses. The semiconductor structure further includes second recesses formed in the substrate adjacent to the second gate structure and second strained source and drain structures formed in the second recesses. In addition, each of the first recesses has a shape of a trapezoid, and each of the second recesses has a shape of an inverted trapezoid.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括衬底和形成在衬底上的第一栅极结构和第二栅极结构。 半导体结构还包括形成在与第一栅极结构相邻的衬底中的第一凹部和形成在第一凹槽中的第一应变源极和漏极结构。 半导体结构还包括形成在基板中的与第二栅极结构相邻的第二凹槽和形成在第二凹槽中的第二应变源极和漏极结构。 另外，每个第一凹部具有梯形的形状，并且每个第二凹部具有倒梯形的形状。

公开(公告)号：US09553171B2

公开(公告)日：2017-01-24

申请号：US14180932

申请日：2014-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Yung-Jung Chang

IPC: H01L27/088 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

Abstract: Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The FinFET device structure includes a substrate and a first fin structure extending above the substrate. The FinFET also includes a first transistor formed on the first fin structure. The first transistor includes a first gate dielectric layer conformally formed on the first fin structure and a first gate electrode formed on the first gate dielectric layer. The FinFET further includes an inter-layer dielectric (ILD) structure formed adjacent to the first transistor. The first gate electrode is in direct contact with a sidewall of the ILD structure.

Abstract translation: 提供了用于形成鳍状场效应晶体管（FinFET）器件结构的实施例。 FinFET器件结构包括衬底和在衬底上延伸的第一鳍结构。 FinFET还包括形成在第一鳍结构上的第一晶体管。 第一晶体管包括保形地形成在第一鳍结构上的第一栅介质层和形成在第一栅介质层上的第一栅电极。 FinFET还包括与第一晶体管相邻形成的层间电介质（ILD）结构。 第一栅电极与ILD结构的侧壁直接接触。

公开(公告)号：US09508719B2

公开(公告)日：2016-11-29

申请号：US14554682

申请日：2014-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Tung-Wen Cheng ,  Che-Cheng Chang ,  Chun-Lung Ni ,  Jr-Jung Lin ,  Chih-Han Lin

IPC: H01L27/092 ,  H01L27/088 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L21/033 ,  H01L21/3213

CPC classification number: H01L21/0338 ,  H01L21/0206 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm.

Abstract translation: 提供了一种用于形成FinFET器件结构的鳍式场效应晶体管（FinFET）器件结构和方法。 FinFET器件结构包括衬底和在衬底上方延伸的第一鳍结构和第二鳍结构。 FinFET器件结构还包括形成在第一鳍结构上的第一晶体管和形成在第二鳍结构上的第二晶体管。 FinFET器件结构还包括形成在第一晶体管和第二晶体管之间的端到端间隙中的层间电介质（ILD）结构，并且端对端间隙具有在约20° nm至约40nm。