公开(公告)号：US11842932B2

公开(公告)日：2023-12-12

申请号：US17739899

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L21/82385 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/30608 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795

Abstract: A method includes providing a substrate having a channel region, forming a gate stack layer over the channel region, forming a patterned hard mask over the gate stack layer, etching a top portion of the gate stack layer through openings in the patterned hard mask with a first etchant, etching a middle portion and a bottom portion of the gate stack layer with a second etchant that includes a passivating gas. A gate stack is formed with a passivation layer deposited on sidewalls of the gate stack. The method also includes etching the gate stack with a third etchant, thereby removing a bottom portion of the passivation layer and recessing a bottom portion of the gate stack.

公开(公告)号：US11764222B2

公开(公告)日：2023-09-19

申请号：US17567476

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Yun-Ting Chou ,  Chih-Han Lin ,  Jr-Jung Lin

IPC: H01L21/311 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/31111 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/66545

Abstract: An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.

公开(公告)号：US20230253470A1

公开(公告)日：2023-08-10

申请号：US18301554

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng Lai ,  Yu-Fan Peng ,  Li-Ting Chen ,  Yu-Shan Lu ,  Yu-Bey Wu ,  Wei-Chung Sun ,  Yuan-Ching Peng ,  Kuei-Yu Kao ,  Shih-Yao Lin ,  Chih-Han Lin ,  Pei-Yi Liu ,  Jing Yi Yan

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42376 ,  H01L21/82385 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/0665 ,  H01L29/785 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78642

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

公开(公告)号：US11699701B2

公开(公告)日：2023-07-11

申请号：US16845102

申请日：2020-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/0886 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7855 ,  H01L21/845 ,  H01L27/1211 ,  H01L2029/7858

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

公开(公告)号：US11652003B2

公开(公告)日：2023-05-16

申请号：US17682621

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng Lai ,  Wei-Chung Sun ,  Li-Ting Chen ,  Kuei-Yu Kao ,  Chih-Han Lin

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/033

CPC classification number: H01L21/823431 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823437

Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.

公开(公告)号：US11557590B2

公开(公告)日：2023-01-17

申请号：US16899268

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng Lai ,  Wei-Chung Sun ,  Li-Ting Chen ,  Kuei-Yu Kao ,  Chih-Han Lin

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.

公开(公告)号：US20220384263A1

公开(公告)日：2022-12-01

申请号：US17818608

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.

公开(公告)号：US11508849B2

公开(公告)日：2022-11-22

申请号：US16915500

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Kai-Yu Cheng ,  Chih-Han Lin ,  Sin-Yi Yang ,  Horng-Huei Tseng

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.

公开(公告)号：US11508825B2

公开(公告)日：2022-11-22

申请号：US16927958

申请日：2020-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L27/108 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/311

Abstract: A Fin FET semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The Fin FET device also includes a gate stack including a gate electrode layer, a gate dielectric layer, side wall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the side wall insulating layers. The gate stack is disposed over the isolation insulating layer, covers a portion of the fin structure, and extends in a second direction perpendicular to the first direction. A recess is formed in an upper surface of the isolation insulating layer not covered by the side wall insulating layers and the interlayer dielectric layers. At least part of the gate electrode layer and the gate dielectric layer fill the recess.

公开(公告)号：US20220328420A1

公开(公告)日：2022-10-13

申请号：US17852806

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng Lai ,  Wei-Chung Sun ,  Li-Ting Chen ,  Kuei-Yu Kao ,  Chih-Han Lin

IPC: H01L23/544 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/8234

Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.