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    CIRCUIT BOARD AND DISPLAY DEVICE INCLUDING THE SAME
    301.
    发明申请
    CIRCUIT BOARD AND DISPLAY DEVICE INCLUDING THE SAME 有权
    电路板和显示装置，包括它们

    公开(公告)号：US20090184910A1

    公开(公告)日：2009-07-23

    申请号：US12186348

    申请日：2008-08-05

    Applicant: Sung-Kyu LEE ,  On-Sik Choi ,  Do-Wan Kim ,  Sung-Wook Kang

    Inventor： Sung-Kyu LEE ,  On-Sik Choi ,  Do-Wan Kim ,  Sung-Wook Kang

    IPC: G09G3/36 ,  H05K7/06

    CPC classification number: H05K1/0245 ,  H05K1/0228 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09672 ,  H05K2201/097

    Abstract: One or more embodiments of the present disclosure relate to a circuit board having a substrate and a plurality of differential signal lines formed on the substrate and transmitting differential signals. The differential signal lines include a first signal line and a second signal line. The first signal line and the second signal line extend along at least two paths that are parallel to each other. The paths of the first signal line and the second signal line switch at path change portions, and the path change portions of neighboring differential signal lines are positioned at different distances away from an edge of the circuit board along the length direction of the differential signal line.

    Abstract translation: 本公开的一个或多个实施例涉及具有衬底和形成在衬底上并传输差分信号的多个差分信号线的电路板。 差分信号线包括第一信号线和第二信号线。 第一信号线和第二信号线沿着彼此平行的至少两个路径延伸。 第一信号线和第二信号线开关在路径改变部分的路径，并且相邻差分信号线的路径变化部分位于与差分信号线的长度方向上离电路板边缘不同的距离处 。

    Multilayer printed circuit board having via arrangements for reducing crosstalk among vias
    302.
    发明授权
    Multilayer printed circuit board having via arrangements for reducing crosstalk among vias 失效
    具有用于减小通孔之间串扰的通孔装置的多层印刷电路板

    公开(公告)号：US07521637B2

    公开(公告)日：2009-04-21

    申请号：US11297303

    申请日：2005-12-08

    Applicant: Don A. Gilliland

    Inventor： Don A. Gilliland

    IPC: H01R12/04 ,  H05K1/11 ,  H01K3/10

    CPC classification number: H05K1/115 ,  H05K1/0216 ,  H05K2201/09245 ,  H05K2201/09836 ,  Y10T29/49167

    Abstract: A printed circuit board having via arrangements for reducing crosstalk is disclosed. The printed circuit board includes a first layer and a second layer. The printed circuit board also includes a first via and a second via, both traveling from the first layer to the second layer. The first via is orthogonal to the second via in a three dimensional space. In addition, the printed circuit board may include a third via traveling from the first layer to the second layer, and the third via is orthogonal to the first and second vias in the three dimensional space.

    Abstract translation: 公开了一种具有用于减少串扰的通孔装置的印刷电路板。 印刷电路板包括第一层和第二层。 印刷电路板还包括从第一层传播到第二层的第一通孔和第二通孔。 第一通孔在三维空间中与第二通孔正交。 此外，印刷电路板可以包括从第一层传播到第二层的第三通孔，并且第三通孔与三维空间中的第一和第二通孔正交。

    Memory-module board layout for use with memory chips of different data widths
    306.
    发明授权
    Memory-module board layout for use with memory chips of different data widths 有权
    内存模块板布局，用于不同数据宽度的内存芯片

    公开(公告)号：US07414312B2

    公开(公告)日：2008-08-19

    申请号：US10908718

    申请日：2005-05-24

    Applicant: Henry H. D. Nguyen ,  Mark Burlington

    Inventor： Henry H. D. Nguyen ,  Mark Burlington

    IPC: H01L23/34 ,  H05K7/00 ,  G11C5/06

    CPC classification number: G11C5/04 ,  G11C8/12 ,  G11C2029/1804 ,  H01L2924/0002 ,  H05K1/181 ,  H05K2201/09245 ,  H05K2201/09954 ,  H05K2201/10689 ,  H05K2203/1572 ,  Y02P70/611 ,  H01L2924/00

    Abstract: A memory module substrate printed-circuit board (PCB) has multi-type footprints and an edge connector for mating with a memory module socket on a motherboard. Two or more kinds of dynamic-random-access memory (DRAM) chips with different data I/O widths can be soldered to solder pads around the multi-type footprints. When ×4 DRAM chips with 4 data I/O pins are soldered over the multi-type footprints, the memory module has a rank-select signal that drives chip-select inputs to all DRAM chips. When ×8 DRAM chips with 8 data I/O pins are soldered over the multi-type footprints, the memory module has two rank-select signals. One rank-select drives chip-select inputs to front-side DRAM chips while the second rank-select drives chip-select inputs to back-side DRAM chips. Wiring traces on the PCB cross-over data nibbles between the solder pads and the connector to allow two ×4 chips to drive a byte driven by only one ×8 chip.

    Abstract translation: 存储器模块基板印刷电路板（PCB）具有多种类型的印迹和用于与主板上的存储器模块插座配合的边缘连接器。 可以将具有不同数据I / O宽度的两种或更多种动态随机存取存储器（DRAM）芯片焊接到多类型脚印周围的焊盘。 当具有4个数据I / O引脚的x4 DRAM芯片通过多种封装焊接时，存储器模块具有驱动芯片选择输入到所有DRAM芯片的等级选择信号。 当具有8个数据I / O引脚的x8 DRAM芯片通过多种封装焊接时，存储器模块具有两个等级选择信号。 一级选择驱动芯片选择输入到前端DRAM芯片，而第二级选择驱动芯片选择输入到后端DRAM芯片。 PCB交叉数据上的接线迹线在焊盘和连接器之间勉强化，以允许两个x4芯片驱动一个仅由一个x8芯片驱动的字节。

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