公开(公告)号：US12176029B2

公开(公告)日：2024-12-24

申请号：US17980382

申请日：2022-11-03

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Lingming Yang ,  John F. Schreck

IPC: G11C7/10 ,  G11C13/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: Systems, methods and apparatus to read target memory cells having an associated reference memory cell configured to be representative of drift or changes in the threshold voltages of the target memory cells. The reference cell is programmed to a predetermined threshold level when the target cells are programmed to store data. In response to a command to read the target memory cells, estimation of a drift of the threshold voltage of the reference is performed in parallel with applying an initial voltage pulse to read the target cells. Based on a result of the drift estimation, voltage pulses used to read the target cells can be modified and/or added to account for the drift estimated using the reference cell.

公开(公告)号：US12175133B2

公开(公告)日：2024-12-24

申请号：US18420887

申请日：2024-01-24

Applicant: Micron Technology, Inc.

Inventor： Daniel James Gunderson

IPC: G06F3/06 ,  G06F11/14

Abstract: Methods, systems, and devices for predictive media management for read disturb are described. A read disturbance manager can monitor a bit error rate for a block of a memory die. The read disturbance manager can detect that a degradation of the bit error rate satisfies a degradation threshold specific to the memory die. In some cases, the read disturbance manager can perform a write operation to write data from the block of the memory die to a second block of the memory die based on detecting that the degradation of the bit error rate satisfies the degradation threshold.

公开(公告)号：US12175130B2

公开(公告)日：2024-12-24

申请号：US18152063

申请日：2023-01-09

Applicant: Micron Technology, Inc.

Inventor： Shanyuan Gao ,  Sen Ma ,  Moon Mark Hur ,  Jaime Cummins

IPC: G06F3/06

Abstract: Methods, systems, and apparatuses related to computational storage are described. For example, storage accessible to an accelerator may be shared between and, accessible to either of, a host and the accelerator. A computational storage system may include storage providing a portion of a shared file system accessible by a host and by accelerator logic of the computational storage system. Host interface logic may be configured to receive a storage command from the host to store data on the storage at a time the data is created. The host interface logic may be further configured to receive a storage command from the host for the accelerator logic to perform a computational task using the stored data on the storage. The accelerator logic can perform the computational task using the stored data on the storage.

公开(公告)号：US20240420789A1

公开(公告)日：2024-12-19

申请号：US18638379

申请日：2024-04-17

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Eric J. Stave ,  Timothy M. Hollis ,  Chulkyu Lee ,  Chris Gregory Holub

IPC: G11C29/12 ,  G11C29/20

Abstract: Systems and methods include self-training an equalizer of a semiconductor device using the semiconductor device. The semiconductor device receives an indication of a condition for re-training of the equalizer. The semiconductor device operates the equalizer based on trained values derived during the self-training. The semiconductor device also determines that the condition has been met, and in response, the semiconductor device re-trains the equalizer without invocation of re-training by a host device coupled to the semiconductor device.

公开(公告)号：US20240420783A1

公开(公告)日：2024-12-19

申请号：US18820480

申请日：2024-08-30

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung LIEN ,  Zhenming ZHOU ,  Tomer Tzvi ELIASH

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/24 ,  G11C16/32

Abstract: Implementations described herein relate to detecting a memory write reliability risk without using a write verify operation. In some implementations, a memory device may perform a program operation that includes a single program pulse and that does not include a program verify operation immediately after the single program pulse. The memory device may set a flag value based on comparing a transition time and a transition time threshold. The transition time may be a time to transition from a first voltage to a second voltage during the program operation. The memory device may selectively perform a mitigation operation based on whether the flag value is set to a first value or a second value.

公开(公告)号：US20240420746A1

公开(公告)日：2024-12-19

申请号：US18814826

申请日：2024-08-26

Applicant: Micron Technology, Inc.

Inventor： Brian W. Huber ,  Scott E. Smith ,  Gary L. Howe

IPC: G11C7/10

Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.

公开(公告)号：US20240419549A1

公开(公告)日：2024-12-19

申请号：US18821203

申请日：2024-08-30

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Helena Caminal ,  Sean S. Eilert

IPC: G06F11/10

Abstract: Methods, systems, and devices for parity-based error management are described. A processing system that performs a computational operation on a set of operands may perform a computational operation, (e.g., the same computational operation) on parity bits for the operands. The processing system may then use the parity bits that result from the computational operation on the parity bits to detect, and discretionarily correct, one or more errors in the output that results from the computational operation on the operands.

公开(公告)号：US20240419534A1

公开(公告)日：2024-12-19

申请号：US18819616

申请日：2024-08-29

Applicant: Micron Technology, Inc.

Inventor： Christopher Baronne

IPC: G06F11/07 ,  G06F9/38

Abstract: Devices and techniques for parking threads in a barrel processor for managing hazard clearing are described herein. A barrel processor includes hazard management circuitry that is used to receive an indication of an instruction executing in a compute pipeline of the barrel processor, the instruction having encountered a hazard and unable to progress through the compute pipeline; store the indication of the instruction in a hazard memory; receive a signal indicating that the hazard has cleared; and cause the instruction to be rescheduled at the beginning of the compute pipeline in response to the signal.

公开(公告)号：US20240419523A1

公开(公告)日：2024-12-19

申请号：US18821283

申请日：2024-08-30

Applicant: Micron Technology, Inc.

Inventor： Shakeel Isamohiuddin BUKHARI ,  Mark ISH

IPC: G06F11/00 ,  G06F12/02 ,  G06F12/12

Abstract: In some implementations, a memory device may cache a subset of one or more block family error avoidance (BFEA) lookup tables associated with a block family associated with host data in a first memory location. The block family may be based on at least one of a time window during which the host data was written or a temperature window at which the host data was written. The memory device may receive a read command associated with host data and determine, based on the block family and the subset of the one or more BFEA tables, a threshold voltage offset associated with the host data. The memory device may compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the host data. The memory device may read, using the modified threshold voltage, the host data from the first memory location.

公开(公告)号：US12171101B2

公开(公告)日：2024-12-17

申请号：US17822708

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Matthew J. King ,  Jordan D. Greenlee ,  Yongjun J. Hu ,  Tom George ,  Amritesh Rai ,  Sidhartha Gupta ,  Kyle A. Ritter

IPC: H10B41/30 ,  H01L21/28 ,  H01L29/49 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/30 ,  H10B43/40

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.