公开(公告)号：US08995160B2

公开(公告)日：2015-03-31

申请号：US14280955

申请日：2014-05-19

Applicant: STMicroelectronics S.A.

Inventor： Olivier Menut ,  David Turgis ,  Lorenzo Ciampolini

IPC: G11C15/00 ,  G11C15/04

CPC classification number: G11C15/046 ,  G11C15/04

Abstract: Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of one of the reference data words; the cells of a given column are dedicated to the comparison of the same bit of the input data word; each cell incorporates: two memory points storing the data representing the reference data bit; a comparison circuit connected to the memory points, with a comparison point of which the potential represents the comparison if the input data bit and the data stored in the memory points, and also incorporating a common comparison circuit to which are connected the comparison circuits of all or part of the cells of a given column; the comparison circuit incorporates terminals to which the bit from the input data word and its complement are applied.

Abstract translation: 电子部件，包括三元内容可寻址存储器部件，被配置为将输入数据项与一组预先记录的参考数据字进行比较; 存储器组件包含以行和列布置的基本单元矩阵; 每行包含单元，每个单元记录一个参考数据字的一位; 给定列的单元专门用于比较输入数据字的相同位; 每个单元包含：存储表示参考数据位的数据的两个存储点; 连接到存储点的比较电路，如果输入数据位和存储在存储点中的数据，电位代表比较的比较点，并且还结合有公共比较电路，连接到所有比较电路的所有比较电路 或给定色谱柱的一部分细胞; 比较电路结合了来自输入数据字及其补码的位的终端。

公开(公告)号：US20140363953A1

公开(公告)日：2014-12-11

申请号：US14298073

申请日：2014-06-06

Applicant: STMicroelectronics S.A.

Inventor： Didier Dutartre

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/16

CPC classification number: H01L29/78 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66575 ,  H01L29/78684 ,  H01L29/78687

Abstract: A method for manufacturing components on an SOI layer coated with a silicon-germanium layer formed by epitaxial deposition, wherein the heat balance of the anneals performed after the epitaxial deposition is such that the germanium concentration remains higher in the silicon-germanium layer than in the SOI layer.

Abstract translation: 一种用于在外延沉积形成的涂覆有硅 - 锗层的SOI层上制造部件的方法，其中在外延沉积之后执行的退火的热平衡使得硅 - 锗层中的锗浓度保持在比在 SOI层。

公开(公告)号：US20140325181A1

公开(公告)日：2014-10-30

申请号：US14329226

申请日：2014-07-11

Applicant: STMicroelectronics S.A.

Inventor： Joël Cambonie

IPC: G06F15/78 ,  G06F15/80

CPC classification number: G06F15/7867 ,  G06F9/3885 ,  G06F13/368 ,  G06F15/173 ,  G06F15/17381 ,  G06F15/803

Abstract: A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels include a first level including a first computation block including a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting mechanism, each computing node including an input port, a functional unit and an output port, the first connecting mechanism capable of connecting each output port to the input port of each other computing node; and a second level including a second computation block including a second data input, a second data output and a plurality of the first computation blocks interconnected by a second connecting means for selectively connecting the first data output of each of the first computation blocks and the second data input to each of the first data inputs and for selectively connecting each of the first data outputs to the second data output.

Abstract translation: 一种具有N个级别的可重构分层计算机架构，其中N是大于1的整数值，其中所述N个级别包括第一级，包括第一计算块，所述第一级包括第一数据输入，第一数据输出和多个计算节点， 第一连接机构，每个计算节点包括输入端口，功能单元和输出端口，所述第一连接机构能够将每个输出端口连接到彼此的计算节点的输入端口; 以及第二级，包括第二计算块，包括第二数据输入，第二数据输出和通过第二连接装置互连的多个第一计算块，用于选择性地连接每个第一计算块和第二计算块的第一数据输出 数据输入到每个第一数据输入端，并且用于选择性地将每个第一数据输出连接到第二数据输出。

公开(公告)号：US20140246723A1

公开(公告)日：2014-09-04

申请号：US14193833

申请日：2014-02-28

Applicant: Commissariat à I'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics S.A.

Inventor： YVES MORAND ,  Romain Wacquez ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Maud Vinet

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7856

Abstract: A method for manufacturing a fin MOS transistor from an SOI-type structure including a semiconductor layer on a silicon oxide layer coating a semiconductor support, this method including the steps of: a) forming, from the surface of the semiconductor layer, at least one trench delimiting at least one fin in the semiconductor layer and extending all the way to the surface of the semiconductor support; b) etching the sides of a portion of the silicon oxide layer located under the fin to form at least one recess under the fin; and c) filling the recess with a material selectively etchable over silicon oxide.

Abstract translation: 一种从包括半导体载体的氧化硅层上的半导体层的SOI型结构制造鳍式MOS晶体管的方法，该方法包括以下步骤：a）从半导体层的表面形成至少一个 沟槽，限定半导体层中的至少一个翅片，并一直延伸到半导体支撑体的表面; b）蚀刻位于翅片下方的氧化硅层的一部分的侧面，以在翅片下方形成至少一个凹部; 以及c）用在氧化硅上可选择性地蚀刻的材料填充所述凹部。

公开(公告)号：US20140217520A1

公开(公告)日：2014-08-07

申请号：US14169913

申请日：2014-01-31

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles 2) SAS ,  Commissariat à I'Énergie Atomique et aux Énergies Alternatives

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Cyrille Le Royer

IPC: H01L29/49 ,  H01L21/28

CPC classification number: H01L29/49 ,  H01L21/28008 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4925 ,  H01L29/4991 ,  H01L29/6653

Abstract: A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion.

Abstract translation: 一种MOS晶体管，包括在栅极绝缘体上方的具有高度，长度和宽度的导电栅极堆叠，该堆叠具有靠近栅绝缘体的下部和上部，其中堆叠具有第一长度 下部，并且在其上部比第一长度短的第二长度。

公开(公告)号：US20140097464A1

公开(公告)日：2014-04-10

申请号：US13796753

申请日：2013-03-12

Applicant: STMicroelectronics S.A.

Inventor： Jean Jimenez ,  Philippe Galy ,  Boris Heitz

IPC: H01L27/02

CPC classification number: H01L27/0259 ,  H01L27/0262 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/87

Abstract: The component incorporates, in topological terms, a scalable number of triac structures in a concentric annular arrangement. The component can be used with an electronic device to protect against electrostatic discharges. For example, the components can be used to protect the input/output pad, the first power supply terminal, and the second power supply terminal of an integrated circuit against electrostatic discharges.

Abstract translation: 该组件以拓扑学方式并入具有同步环形布置的可缩放数量的三端双向可控硅结构。 该组件可与电子设备一起使用，以防止静电放电。 例如，这些组件可用于保护集成电路的输入/输出焊盘，第一电源端子和第二电源端子免受静电放电。

公开(公告)号：US20140070331A1

公开(公告)日：2014-03-13

申请号：US14084803

申请日：2013-11-20

Applicant: STMicroelectronics S.A. ,  International Business Machines Corporation

Inventor： Erwan Dornel ,  Pascal R. Tannhof ,  Denis Rideau

IPC: H01L29/78 ,  H01L29/51

CPC classification number: H01L29/401 ,  H01L21/28247 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/512 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure.

Abstract translation: 一种制造半导体器件的方法，包括在半导体衬底的沟道部分上提供栅极结构，其中栅极结构包括在半导体衬底的沟道部分上的至少一个栅极电介质和至少一个栅极导体 栅电介质。 至少一个栅极电介质的边缘部分在栅极结构的每一侧被去除，其中去除栅极电介质的边缘部分提供至少一个栅极导体的暴露的基极边缘和暴露的沟道表面 栅极结构底层的半导体衬底。 栅极结构的侧壁被氧化，其还氧化至少一个栅极导体的暴露的基极边缘和位于栅极结构下方的半导体衬底的暴露的沟道表面中的至少一个。

公开(公告)号：US20130335297A1

公开(公告)日：2013-12-19

申请号：US13920237

申请日：2013-06-18

Applicant: Commissariat à I'Ènergie Atomique et aux 'Ènergies Alternatives ,  STMicroelectronics S.A.

Inventor： Pierre Bar ,  Laurent Dussopt ,  Jean-François Carpentier

IPC: H01Q1/50

CPC classification number: H01L23/66 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/15788 ,  H01Q1/243 ,  H01Q1/50 ,  H01Q9/0457 ,  H01Q13/106 ,  H01Q19/10 ,  H01Q23/00 ,  H04B1/3833 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941

Abstract: The three-dimensional integrated structure including a support element, an interface device connected to the support element by first electrically conductive connection, an integrated circuit arranged between the support element and the interface device and connected to the interface device by second electrically conductive connection, a filler region between the second electrically conductive connection and between the interface device and the integrated circuit, and an antenna, having a radiating element in electromagnetic coupling with an excitation element through the interconnection of a slot, the antenna being distributed over the interface device and the integrated circuit.

Abstract translation: 三维一体化结构包括支撑元件，通过第一导电连接连接到支撑元件的接口装置，布置在支撑元件和接口装置之间并通过第二导电连接连接到接口装置的集成电路， 所述第二导电连接之间和所述接口装置与所述集成电路之间的填充区域，以及天线，所述天线具有通过所述插槽的互连与激励元件电磁耦合的辐射元件，所述天线分布在所述接口装置上， 集成电路。

公开(公告)号：US20130295734A1

公开(公告)日：2013-11-07

申请号：US13871884

申请日：2013-04-26

Applicant: STMicroelectronics S.A. ,  Commissariat a l'Energie Atomique et aux Energies Alternatives

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Cyrille Le Royer ,  Fabrice Nemouchi

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/28247 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823475 ,  H01L21/84 ,  H01L29/66545 ,  H01L29/66606

Abstract: A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer.

Abstract translation: 一种用于在MOS晶体管上形成栅极，源极和漏极接触的方法，其具有包括被金属栅极硅化物覆盖的多晶硅的绝缘栅极，该栅极由至少一个由第一绝缘材料制成的隔离物包围，该方法包括以下步骤： a）用第二绝缘材料覆盖结构并使第二绝缘材料平整以到达栅极硅化物; b）氧化栅极，使得栅极硅化物掩埋并覆盖氧化硅; c）选择性地去除所述第二绝缘材料; 以及d）用第一导电材料覆盖所述结构，并且将所述第一导电材料一直调整到所述隔离物顶部的较低水平。

公开(公告)号：US20130196500A1

公开(公告)日：2013-08-01

申请号：US13748126

申请日：2013-01-23

Applicant: STMicroelectronics S.A. ,  Commissariat a l'Energie Atomique et aux Energies Alternatives

Inventor： Perrine Batude ,  Yves Morand

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76897 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823475

Abstract: A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material.

Abstract translation: 一种用于形成连接第一上层与第二下层的通孔的方法，所述两层被绝缘材料包围，所述方法包括以下步骤：a）形成开口以到达第一层的边缘， 横向延伸超过所述边缘; b）仅在所述边缘上形成保护材料层; c）通过选择性地蚀刻绝缘材料到达第二较低层来加深所述开口; 以及d）用至少一个导电接触材料填充该开口。