公开(公告)号：US20180204627A1

公开(公告)日：2018-07-19

申请号：US15924100

申请日：2018-03-16

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C16/34 ,  G11C16/28 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

Abstract: The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

公开(公告)号：US09997252B2

公开(公告)日：2018-06-12

申请号：US15706586

申请日：2017-09-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiao Yan Pi ,  Xiaozhou Qian ,  Kai Man Yue ,  Yao Zhou ,  Yaohua Zhu

IPC: G11C16/06 ,  G11C16/28 ,  G11C16/08 ,  G11C7/14 ,  G11C16/24 ,  G11C7/06 ,  G11C29/02 ,  G11C7/12 ,  G11C29/12 ,  G11C29/50

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C16/08 ,  G11C16/24 ,  G11C29/025 ,  G11C2029/1204 ,  G11C2029/5006

Abstract: An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.

公开(公告)号：US09972632B2

公开(公告)日：2018-05-15

申请号：US15476663

申请日：2017-03-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Nhan Do

IPC: H01L27/11521 ,  H01L29/423 ,  G11C16/10 ,  G11C16/16

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328

Abstract: A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region adjacent to the first region. A second floating gate is disposed over and insulated from a second portion of the channel region adjacent to the second region. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. A first erase gate disposed over and insulated from the first region. A second erase gate disposed is over and insulated from the second region.

公开(公告)号：US09922715B2

公开(公告)日：2018-03-20

申请号：US14506433

申请日：2014-10-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

IPC: G11C16/14 ,  G11C16/24 ,  G11C16/04 ,  G11C16/26 ,  G11C16/12 ,  G11C16/10

CPC classification number: G11C16/24 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

Abstract: A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage. A control circuit receives a command signal and generates a plurality of control signals, in response thereto and applies the first negative voltage to the word line of the unselected memory cells. During the operations of program, read or erase, a negative voltage can be applied to the word lines of the unselected memory cells.

公开(公告)号：US09911501B2

公开(公告)日：2018-03-06

申请号：US15163548

申请日：2016-05-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C16/06 ,  G11C16/28 ,  G11C16/14 ,  G11C16/24

CPC classification number: G11C16/28 ,  G11C7/065 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/24

Abstract: The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, the sensing amplifier includes a built-in voltage offset. In another embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors. In another embodiment, the sensing amplifier utilizes sloped timing for the reference signal to increase the margin by which a “0” or “1” are detected from the current drawn by the selected cell compared to the reference cell. In an another embodiment, a sensing amplifier is used without any voltage offset.

公开(公告)号：US20170338330A1

公开(公告)日：2017-11-23

申请号：US15494499

申请日：2017-04-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L27/11521 ,  H01L21/3213

CPC classification number: H01L29/66825 ,  H01L21/32133 ,  H01L27/11521 ,  H01L29/42328

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US20170337980A1

公开(公告)日：2017-11-23

申请号：US15374588

申请日：2016-12-09

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Xinjie Guo ,  Farnood Merrikh Bayat ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11558 ,  H01L27/11521

CPC classification number: G11C16/3431 ,  G11C7/18 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11558 ,  H01L29/7881

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

公开(公告)号：US20170317093A1

公开(公告)日：2017-11-02

申请号：US15476663

申请日：2017-03-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Nhan Do

IPC: H01L27/11521 ,  G11C16/10 ,  G11C16/16 ,  H01L29/423

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328

Abstract: A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region adjacent to the first region. A second floating gate is disposed over and insulated from a second portion of the channel region adjacent to the second region. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. A first erase gate disposed over and insulated from the first region. A second erase gate disposed is over and insulated from the second region.

公开(公告)号：US20170316823A1

公开(公告)日：2017-11-02

申请号：US15404087

申请日：2017-01-11

Applicant: Silicon Storage Technology, Inc. ,  Agency For Science, Technology And Research

Inventor： Feng Zhou ,  XIAN LIU ,  NHAN DO ,  HIEU VAN TRAN ,  HUNG QUOC NGUYEN ,  MARK REITEN ,  ZHIXIAN CHEN ,  WANG XINPENG ,  GUO-QIANG LO

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0007 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in time across the first and second electrodes. For each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.

公开(公告)号：US09793281B2

公开(公告)日：2017-10-17

申请号：US15180376

申请日：2016-06-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Feng Zhou

IPC: H01L27/115 ,  H01L27/11531 ,  H01L27/11524 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11521

CPC classification number: H01L27/11531 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66484 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.