公开(公告)号：US20240377587A1

公开(公告)日：2024-11-14

申请号：US18783031

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen

IPC: G02B6/13 ,  G02B6/12 ,  G02B6/124 ,  H01L21/56 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528

Abstract: A packaged device includes an optical IC having an optical feature therein. An interconnect structure including layers of conductive features embedded within respective layers of dielectric materials overlie the optical feature. The interconnect structure is patterned to remove the interconnect structure from over the optical feature and a dielectric material having optically neutral properties, relative to a desired light wavelength(s) is formed over the optical feature. One or more electronic ICs may be bonded to the optical IC to form an integrated package.

公开(公告)号：US12144065B2

公开(公告)日：2024-11-12

申请号：US17869384

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Wei-Yu Chen ,  Chien-Wei Lee ,  Chung-Shi Liu

IPC: B23K3/08 ,  H01L21/677 ,  H01L21/68 ,  H01L21/683 ,  H01L23/00 ,  H05B3/02 ,  B23K101/40

Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.

公开(公告)号：US12140802B2

公开(公告)日：2024-11-12

申请号：US17334365

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Wei Kuo

IPC: G02B6/34 ,  G02B6/30

Abstract: A grating coupler integrated in a photonically-enabled circuit and a method for fabricating the same are disclosed herein. In some embodiments, the grating coupler includes a substrate comprising a silicon wafer, a first grating region etched into the substrate, wherein the first grating region comprises a first plurality of gratings having a first predetermined height, and a second grating region etched into the substrate, wherein the second grating region comprises a second plurality of gratings having a second predetermined height and wherein the first and second predetermined heights are not identical.

公开(公告)号：US12138735B2

公开(公告)日：2024-11-12

申请号：US16559472

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chung Chen ,  Yi-Shao Lin ,  Sheng-Tai Peng ,  Ya-Jen Sheuh ,  Hung-Lin Chen ,  Ren-Dou Lee

IPC: B24B37/20 ,  B24B37/013 ,  B24B37/04 ,  C09G1/02

Abstract: Described herein are multi-layered windows for use in chemical-mechanical planarization (CMP) systems and CMP processes. The multi-layered windows of the present disclosure include a transparent structural layer and a hydrophilic surfactant applied to at least a portion of at least one surface of the transparent structural layer. Such multi-layered windows may be in the polishing pad, the platen, or both.

公开(公告)号：US20240372001A1

公开(公告)日：2024-11-07

申请号：US18778590

申请日：2024-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.

公开(公告)号：US20240372000A1

公开(公告)日：2024-11-07

申请号：US18776388

申请日：2024-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chi Wu ,  Chai-Wei Chang ,  Jung-Jui Li ,  Ya-Lan Chang ,  Yi-Cheng Chao

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.

公开(公告)号：US20240371963A1

公开(公告)日：2024-11-07

申请号：US18770185

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

Abstract: In an embodiment, a device includes: a first channel region; a second channel region; and a gate structure around the first channel region and the second channel region, the gate structure including: a gate dielectric layer; a first p-type work function metal on the gate dielectric layer, the first p-type work function metal including fluorine and aluminum; a second p-type work function metal on the first p-type work function metal, the second p-type work function metal having a lower concentration of fluorine and a lower concentration of aluminum than the first p-type work function metal; and a fill layer on the second p-type work function metal.

公开(公告)号：US20240371867A1

公开(公告)日：2024-11-07

申请号：US18773361

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen HO ,  Chien LIN ,  Tzu-Wei LIN ,  Ju Ru HSIEH ,  Ching-Lun LAI ,  Ming-Kai LO

IPC: H01L27/088 ,  H01L27/092 ,  H10B12/00

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.

公开(公告)号：US20240371859A1

公开(公告)日：2024-11-07

申请号：US18773203

申请日：2024-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jun-De JIN ,  Tzu-Jin YEH

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a substrate, a first metal-oxide-semiconductor device and a at least one first resistor. The substrate includes a non-doped region. The first metal-oxide-semiconductor device extends into the substrate. The first metal-oxide-semiconductor device is adjacent to the non-doped region. The at least one first resistor is disposed right above the non-doped region and arranged in a first row aligned with the first metal-oxide-semiconductor device in a first direction.

公开(公告)号：US20240371708A1

公开(公告)日：2024-11-07

申请号：US18770582

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsiang CHAO ,  Chi-Ping LEI

IPC: H01L21/66 ,  B24B37/005 ,  B24B37/30 ,  H01L21/306

Abstract: A method and system includes: a pad comprising a first side and a second side opposite the first side, wherein the first side is configured to receive a wafer during chemical mechanical planarization (CMP), and a platen adjacent the pad along the second side, wherein the platen comprises a suction opening that interfaces with the second side; a pump configured to produce suction at the suction opening to adhere the second side to the platen; and a sensor configured to collect sensor data characterizing a uniformity of adherence between the pad and the platen, wherein the pump is configured to produce the suction at the suction opening based on the sensor data.