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公开(公告)号：US09912185B2
公开(公告)日：2018-03-06
申请号：US15251899
申请日：2016-08-30
Applicant: STMicroelectronics (Tours) SAS
Inventor： Emilien Bouyssou , Igor Bimbaud
IPC: H02J7/00 , H01M10/44 , H02J7/04 , H01M10/04 , H01M10/052 , H01M10/0562 , H01M10/42 , H01M6/50 , H01M16/00 , H01M10/0525 , H01M10/48 , H02J7/34 , H01M6/40
CPC classification number: H02J7/007 , H01M6/40 , H01M6/5077 , H01M10/0436 , H01M10/052 , H01M10/0525 , H01M10/0562 , H01M10/4242 , H01M10/44 , H01M10/443 , H01M10/486 , H01M16/00 , H02J7/0075 , H02J7/34 , Y02E60/122
Abstract: A method for managing the lifetime of a battery is disclosed herein. An ambient temperature is measured near a battery. The ambient temperature rises above a first threshold and, in response to detecting that the ambient temperature has risen above the first threshold, the battery is discharged. A battery system and a device operable with a battery are also disclosed.
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公开(公告)号：US09859843B2
公开(公告)日：2018-01-02
申请号：US15252868
申请日：2016-08-31
Applicant: STMicroelectronics (Tours) SAS
Inventor： Sylvain Charley , Jerome Heurtier , Laurent Jeuffrault
CPC classification number: H03B5/20 , H01G7/06 , H03B5/124 , H03B2201/011 , H03L7/1075
Abstract: A first capacitor has a capacitance adjustable to a set point value by application of a bias voltage. A second capacitor also has a capacitance adjustable to a set point value by application of a bias voltage. The first and second capacitors are arranged to receive the same bias voltage generated by a control circuit. The control circuit receiving the set point value as an input and generates that bias voltage in response to a quantity representative of a capacitance of the second capacitor.
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公开(公告)号：US20170324350A1
公开(公告)日：2017-11-09
申请号：US15659822
申请日：2017-07-26
Applicant: STMicroelectronics (Tours) SAS
Inventor： Laurent Gonthier , Muriel Nina , Romain Pichon
CPC classification number: H02M7/162 , H02M1/081 , H02M7/062 , H02M7/125 , H02M7/1623
Abstract: An AC/DC converter includes: a first terminal and a second terminal for receiving an AC voltage and a third terminal and a fourth terminal for supplying a DC voltage. A rectifying bridge includes input terminals respectively coupled to the first terminal and the second terminal, and output terminals respectively coupled to the third terminal and fourth terminal. A first branch of the rectifying bridge includes, connected between the output terminals, two series-connected thyristors with a junction point of the two thyristors being connected to a first one of the input terminals. A second branch of the rectifying bridge is formed by series connected diodes. A control circuit is configured to generate control signals for application to the control gates of the thyristors.
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公开(公告)号：US09780188B2
公开(公告)日：2017-10-03
申请号：US15354496
申请日：2016-11-17
Inventor： Samuel Menard , Gael Gautier
IPC: H01L29/747 , H01L29/66 , H01L29/87 , H01L29/06 , H01L21/288 , H01L21/762 , H01L29/32 , H01L29/45
CPC classification number: H01L29/66386 , H01L21/2885 , H01L21/76202 , H01L29/0615 , H01L29/0619 , H01L29/0642 , H01L29/0649 , H01L29/0661 , H01L29/32 , H01L29/456 , H01L29/747 , H01L29/87
Abstract: A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well. The porous silicon ring is produced by forming a doped well in a first surface of a doped substrate, placing that first surface of the substrate into an electrolytic bath, and circulating a current between an opposite second surface of the substrate and the electrolytic bath.
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公开(公告)号：US20170271793A1
公开(公告)日：2017-09-21
申请号：US15610825
申请日：2017-06-01
Applicant: STMicroelectronics (Tours) SAS
Inventor： Arnaud Edet , Christian Nopper
CPC classification number: H01R12/71 , H01R12/716 , H01R13/665 , H05K1/0298 , H05K1/14 , H05K1/185 , H05K2201/047
Abstract: An electrical connector includes a frame delimiting an elongated open cavity, and having two parallel long sides provided with contact areas capable of cooperating with contact areas of a complementary electrical connector. Each long side is formed of a multilayer printed circuit board.
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Patent Agency Ranking
公开(公告)号：US20170170746A1
公开(公告)日：2017-06-15
申请号：US15140163
申请日：2016-04-27
Applicant: STMicroelectronics (Tours) SAS
Inventor： Ghafour Benabdelaziz , Laurent Gonthier
Abstract: A rectifying circuit including: between a first terminal of application of an AC voltage and a first rectified voltage delivery terminal, at least one first diode; and between a second terminal of application of the AC voltage and a second rectified voltage delivery terminal, at least one first anode-gate thyristor, the anode of the first thyristor being connected to the second rectified voltage delivery terminal; and at least one first stage for controlling the first thyristor, including: a first transistor coupling the thyristor gate to a terminal of delivery of a potential which is negative with respect to the potential of the second rectified voltage delivery terminal; and a second transistor connecting a control terminal of the first transistor to a terminal for delivering a potential which is positive with respect to the potential of the second rectified voltage delivery terminal, the anode of the first thyristor being connected to the common potential of voltages defined by said positive and negative potentials.
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公开(公告)号：US20170069883A1
公开(公告)日：2017-03-09
申请号：US14847137
申请日：2015-09-08
Applicant: STMicroelectronics (Tours) SAS
Inventor： Vincent Jarry
CPC classification number: H01M2/0207 , H01M2/026 , H01M2/0277 , H01M2/0285 , H01M2/0287 , H01M2/22 , H01M2/30 , H01M6/40 , H01M10/0436 , H01M10/0463 , H01M2220/30
Abstract: A battery encapsulation method includes disposing an active battery layer on each of a plurality of battery substrates, with each battery substrate having a greater area than its corresponding active battery layer. The plurality of battery substrates are attached to an interposer having a greater area than an aggregate area of the plurality of battery substrates. The active battery layers are environmentally sealed by disposing a film over the active battery layers sized such that the film extends beyond the active battery layers to contact the battery substrates and the interposer. The interposer is physically along locations where the film contacts the interposer so as to form a plurality of battery units, with each battery unit including one of the battery substrates with the associated active battery layer disposed thereon and being environmentally sealed by the film.
Abstract translation: 电池封装方法包括在多个电池基板中的每一个上设置有源电池层，其中每个电池基板具有比其相应的有源电池层更大的面积。 多个电池基板被附接到具有比多个电池基板的集合区域更大的面积的插入件。 活性电池层通过在活性电池层上设置薄膜来进行环境密封，活性电池层的尺寸使得膜延伸超过有源电池层以接触电池基板和插入件。 内插器在物理上沿着膜接触插入件的位置，以便形成多个电池单元，每个电池单元包括其中一个电池基板，其中相关联的有源电池层设置在该电池基板上，并被该膜环境密封。
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公开(公告)号：US20170069733A1
公开(公告)日：2017-03-09
申请号：US15354496
申请日：2016-11-17
Inventor： Samuel Menard , Gael Gautier
IPC: H01L29/66 , H01L21/762 , H01L29/06 , H01L29/32 , H01L21/288 , H01L29/747 , H01L29/45
CPC classification number: H01L29/66386 , H01L21/2885 , H01L21/76202 , H01L29/0615 , H01L29/0619 , H01L29/0642 , H01L29/0649 , H01L29/0661 , H01L29/32 , H01L29/456 , H01L29/747 , H01L29/87
Abstract: A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well. The porous silicon ring is produced by forming a doped well in a first surface of a doped substrate, placing that first surface of the substrate into an electrolytic bath, and circulating a current between an opposite second surface of the substrate and the electrolytic bath.
Abstract translation: 垂直功率部件包括在衬底的下表面上具有第二导电类型的阱的第一导电类型的硅衬底。 第一个阱在具有绝缘多孔硅环的部件周边上界定。 多孔硅环的上表面仅与第一导电类型的基板接触。 绝缘多孔硅环穿透衬底直至深度大于孔的厚度。 多孔硅环通过在掺杂衬底的第一表面中形成掺杂阱，将衬底的第一表面放置在电解槽中并使电流在衬底的相对的第二表面和电解槽之间循环来制造。
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公开(公告)号：US09531187B2
公开(公告)日：2016-12-27
申请号：US15143061
申请日：2016-04-29
Applicant: STMicroelectronics (Tours) SAS
Inventor： Jérôme Heurtier , Guillaume Bougrine , Arnaud Florence
Abstract: An overvoltage protection device capable of protecting a power supply line and including in parallel a break-over diode, a controlled switch, and a circuit for controlling the switch.
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公开(公告)号：US20160373021A1
公开(公告)日：2016-12-22
申请号：US14964618
申请日：2015-12-10
Applicant: STMicroelectronics (Tours) SAS
Inventor： Laurent Gonthier
CPC classification number: H02M7/06 , H02M1/32 , H02M1/36 , H02M1/4208 , H02M7/125 , H02M7/217 , Y02P80/112
Abstract: An AC/DC converter includes a first terminal and a second terminal for receiving an AC voltage and a third terminal and a fourth terminal for delivering a DC voltage. Two transistor switches are series-connected between the third and fourth terminals, with their junction point connected to the first terminal. Two controllable rectifying elements are series-connected between the third and fourth terminals, with their junction point connected to the first terminal or to the second terminal. The two controllable rectifying elements are phase-angle controlled.
Abstract translation: AC / DC转换器包括用于接收AC电压的第一端子和第二端子，以及用于传送DC电压的第三端子和第四端子。 两个晶体管开关串联在第三和第四端子之间，其连接点连接到第一端子。 两个可控整流元件串联在第三和第四端子之间，其连接点连接到第一端子或第二端子。 两个可控整流元件是相位角控制的。
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